Memory Cell Programming With Soft Erase for Charge Loss Control

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Solution Overview

Problem

Existing memory sub-systems face challenges in managing charge loss during programming of memory cells, leading to widened threshold voltage distributions and reduced read window budget due to charge loss mechanisms such as single bit, intrinsic, and quick charge loss, which are not effectively addressed by current techniques.

Innovation Solution

Implementing a push-pull programming operation with a soft erase sub-operation between programming pulses and program verify operations, using a lower erase voltage to accelerate charge loss and improve read window budget.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional programming operations are used without soft erase sub-operations, then programming time is reduced, but charge loss is not effectively managed leading to widened threshold voltage distributions and reduced read window budget

Engineering Contradiction:

Improveread window budgetVSAvoidprogramming time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The programming operation is segmented into multiple phases: programming pulse application, soft erase sub-operation, and program verify. This segmentation allows charge loss to be managed during the soft erase phase while maintaining programming efficiency through the verify phase, resolving the contradiction between reliability and time loss.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The soft erase sub-operation is performed as a preliminary action between programming pulses and program verify operations. This preliminary action accelerates charge loss before the verify operation, ensuring accurate verification while maintaining overall programming time efficiency.

Inventive Principle:

Principle #10Preliminary action

2Manufacturing precision

If charge loss management techniques are implemented to improve read window budget, then programming precision is improved, but device complexity increases

Engineering Contradiction:

Improvethreshold voltage distributionVSAvoidprogramming operation complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The soft erase sub-operation merges the charge loss management function with the existing programming operation structure. By combining these functions into a unified operation sequence, the patent improves threshold voltage distribution without significantly increasing device complexity.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The invention utilizes parameter changes in voltage application during the soft erase sub-operation to manage charge loss. By adjusting voltage parameters dynamically during different phases, the patent achieves precise threshold voltage control without adding complex hardware structures.

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The push-pull programming operation enhances RWB gain and reduces programming time by accelerating charge loss identification and correction during the programming cycle, resulting in improved memory device performance.

Implementation Method 1

Memory cells can be programmed to store data in a logic state. A memory cell may include a floating gate that can be charged or discharged to represent a logic state.

Methodology Applied

Scientific EffectQuantum tunneling:

Implementation Method 2

A programming operation can include applying a programming pulse to a selected wordline to program a set of memory cells to a programming level.

Methodology Applied

Scientific EffectElectron tunneling:

Implementation Method 3

The programming operation includes a soft erase sub-operation between the programming pulse and the program verify operation. The soft erase sub-operation can include applying a lower erase voltage to accelerate charge loss.

Methodology Applied

Scientific EffectReverse tunneling:

Data Source

PatentUS20260011374A1Charge loss acceleration management in a memory sub-system

Publication Date: 2026.01.08 MICRON TECHNOLOGY INC

AI summary

Control logic in a memory device causes a programming pulse of a programming operation to be applied to a selected wordline associated with a plurality of memory cells of a memory device to be programmed to a target voltage level representing a programming level, where a charge loss associated with the plurality of memory cells occurs following application of the programming pulse. The selected wordline is discharged to establish an erase voltage level on the plurality of memory cells and accelerate the charge loss associated with the plurality of memory cells. The control logic performs a program verify operation corresponding to the programming level associated with the plurality of memory cells.