Memory Cell Programming Control for Threshold Voltage Reliability
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Solution Overview
Problem
Nonvolatile memory devices face challenges in maintaining reliability of threshold voltage distribution due to deeply erased memory cells, which affect data retention and performance.
Innovation Solution
The memory device incorporates a control logic circuit that applies different bit line voltages to memory cells based on their programming status, along with sequential selection of word lines, to improve the threshold voltage distribution by removing deeply erased cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional programming is performed on all memory cells, then programming coverage is improved, but threshold voltage distribution reliability deteriorates due to deeply erased cells
Solution Approach 1:
The patent extracts and removes deeply erased memory cells from the programming process. The control logic identifies cells with threshold voltage below the erase reference voltage and excludes them from receiving programming voltages, thereby preventing them from becoming deeply erased and maintaining threshold voltage distribution reliability while still programming other cells
Solution Approach 2:
The patent applies different programming treatments to different memory cells based on their individual threshold voltage states. Cells with threshold voltage above the erase reference voltage receive full programming, while deeply erased cells below the reference voltage are excluded, creating localized quality differentiation to maintain overall reliability
2Reliability
If deeply erased memory cells are removed from programming, then threshold voltage distribution reliability is improved, but programming efficiency deteriorates
Solution Approach 1:
The patent performs preliminary identification of deeply erased cells before the programming operation. The control logic circuit determines which cells have threshold voltage below the erase reference voltage and pre-marks them for exclusion, allowing the programming process to proceed efficiently without attempting to program these problematic cells
Data Source
AI summary
A memory device includes a memory cell array including a plurality of memory cells coupled with a plurality of word lines and a plurality of bit lines, a row decoder circuit configured to select at least one of the plurality of word lines, a voltage generation circuit, a page buffer circuit coupled with the plurality of bit lines, and a control logic circuit configured to control the row decoder circuit, the voltage generation circuit, and the page buffer circuit. The voltage generation circuit is configured to provide a first word line voltage to a selected word line and a second word line voltage to an unselected word line. The page buffer is configured to receive first data to be programmed in the plurality of memory cells, provide a first bit line voltage to a selected bit line, and provide a second bit line voltage to an unselected bit line.