Multi-Bit Memory Programming with Tight Intermediate States
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Non-volatile memory systems face challenges in maintaining performance and durability due to increased erase operations and intercellular disturbances, such as the Yupin effect, which affect read accuracy and memory cell longevity.
Innovation Solution
A non-volatile memory system with multi-bit cells configured to store multiple bits within a threshold window, using a control circuit to program data in both single-bit and multi-bit modes, with target states optimized to minimize field environment asymmetry and reduce program disturb effects, such as the Yupin effect, by employing a multi-pass programming scheme and specific voltage pulse sequences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are operated in multi-bit mode to increase storage density, then data storage capacity is improved, but read accuracy deteriorates due to increased intercellular disturbances and Yupin effect
Solution Approach 1:
The patent segments the programming process into multiple passes, with each pass targeting specific bits of data. This segmentation allows the memory system to program multiple bits sequentially rather than simultaneously, reducing the cumulative intercellular disturbance and Yupin effect on any single bit during verification, thereby maintaining read accuracy while achieving multi-bit storage capacity.
2Reliability
If multiple erase operations are performed to maintain performance, then data retention is improved, but memory cell durability deteriorates due to increased wear
Solution Approach 1:
The patent applies preliminary actions by performing targeted verification and selective re-programming of only those memory cells that require correction, rather than erasing and re-programming entire blocks. This preliminary identification and selective treatment approach maintains data retention for affected cells while minimizing unnecessary erase operations that would accelerate memory cell wear.
3Object-affected harmful factors
If tight intermediate target states are used to reduce program disturb, then intercellular disturbance is reduced, but programming complexity increases
Solution Approach 1:
The patent changes the voltage parameters by introducing tight intermediate target states with specific voltage thresholds between the erased and fully programmed states. These intermediate states serve as stable stopping points during multi-pass programming, reducing the voltage swing and electric field stress on memory cells, thereby minimizing program disturb effects while the multi-pass approach manages the programming complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances memory system durability and performance by reducing the number of erase cycles and mitigating intercellular disturbances, thereby improving data retention and read accuracy across varying field environments.
Implementation Method 1
A charge-storing material such as a conductive floating gate or a non-conductive charge-trapping material can be used in some types of memory cells to store a charge which represents a data state
Implementation Method 2
Additional program voltages may be applied to control gate, followed by verify voltages, until the memory cell's threshold current is within a target range
Implementation Method 3
a memory cell can be electrically erasable, by applying a high voltage to the substrate relative to the control gate so as to induce electrons in the floating gate to tunnel through a thin oxide to the substrate channel region (i.e., Fowler-Nordheim tunneling)
Data Source
AI summary
A non-volatile memory system and corresponding method of operation are provided. The system includes non-volatile memory cells, each retaining a threshold voltage within a threshold window. The non-volatile memory cells include multi-bit cells each configured to store a plurality of bits of data with the threshold window partitioned into bands each having a band width. The bands include a lowest band denoting an erased state and increasing bands. A control circuit programs a first set of the data into the multi-bit cells in a single-bit mode using first target states being one of the erased state and a tight intermediate state having a distribution of the threshold voltage no wider than the band width of one of the increasing bands. The control circuit also programs a second set of the data into the multi-bit cells in a multi-bit mode with each of the multi-bit cells storing the plurality of bits.