Memory Programming Parallelism and Verification Isolation
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Solution Overview
Problem
Current memory system programming methods are inefficient as they often require repetitive program loops for each memory cell, leading to increased programming time and potential overprogramming issues due to simultaneous operations on multiple cells.
Innovation Solution
A method that performs repetitive program loops on selected memory cells, including program and verify operations, where multiple memory cells can be programmed simultaneously using shared word lines and string select lines, with voltage levels increasing stepwise, and verify operations only performed on the selected cell to prevent overprogramming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If repetitive program loops are performed on each memory cell individually, then programming accuracy is maintained, but total programming time increases
Solution Approach 1:
The patent merges the program operations for multiple memory cells by applying program voltage to multiple word lines simultaneously, allowing parallel programming of multiple cells while maintaining individual verify operations for each cell to ensure accuracy
2Productivity
If program voltage is applied to multiple word lines simultaneously, then programming speed increases, but overprogramming risk increases
Solution Approach 1:
The patent segments the verify operation from the program operation, performing verify operations individually on each memory cell after simultaneous program operations, thereby maintaining programming speed while preventing overprogramming through cell-by-cell verification
Solution Approach 2:
The patent implements periodic verify operations interspersed among multiple program loops, where verify operations are performed at specific intervals to check programming status and prevent overprogramming while maintaining overall programming efficiency
3Manufacturing precision
If individual verify operations are performed on each memory cell, then programming accuracy is ensured, but operational complexity increases
Solution Approach 1:
The patent uses a universal verify operation mechanism that can be applied to any selected memory cell regardless of which word line it is connected to, simplifying the control logic by maintaining a consistent verify procedure while accommodating parallel program operations on multiple cells
Data Source
AI summary
A method of programming a memory system includes repetitively performing N program loops for a selected memory cell (where N is a natural number equal to or greater than two). Each of the N program loops includes a program operation and a program verify operation. At least one of the N program loops includes performing the program operation on the selected memory cell and on at least one additionally selected memory cell by applying a program voltage to at least one word line to which the selected memory cell and at least one additionally selected memory cell are connected, and performing the program verify operation on the selected memory cell by applying a program verify voltage to a selected word line to which the selected memory cell is connected.