Memory Cell Programming with Shared Verify Levels

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Solution Overview

Problem

Existing flash memory devices face long programming and verify operation times due to the large number of programming and verify pulses required for multi-level cell operations, particularly in multi-pass programming schemes like 2N-2N schemes, which increase the overall operation time.

Innovation Solution

The solution involves reducing the number of intermediate levels in multi-pass programming operations by combining the threshold voltage ranges of the erase and programming states in a single pass, sharing verify operations, and optimizing the programming voltage steps to reduce the number of pulses, thereby streamlining the programming process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multi-pass programming operations are used to program memory cells into multiple threshold voltage ranges, then the memory cell can store more data (N-bits), but the programming and verify operation time increases significantly

Engineering Contradiction:

Improvedata storage capacityVSAvoidprogramming and verify operation time

Core Design Contradiction:

Quantity of substanceVSLoss of time

Solution Approach 1:

The programming operation is divided into multiple passes, where each pass programs the memory cell into a specific threshold voltage range. The first pass programs into intermediate ranges, and the second pass programs into final ranges, enabling N-bits storage while managing operation time through structured segmentation.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent combines the threshold voltage ranges of erase and programming states into a single pass operation. By merging these ranges and sharing verify operations, the patent reduces the total number of programming and verify pulses required, thereby decreasing operation time while maintaining data storage capacity.

Inventive Principle:

Principle #5Merging (Combining)

2Reliability

If the number of programming pulses is increased to ensure accurate data programming, then the programming completeness improves, but the operation time increases

Engineering Contradiction:

Improveprogramming completenessVSAvoidoperation time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent uses partial programming actions in the first pass by programming into intermediate threshold voltage ranges rather than directly into final ranges. This partial action allows for reduced pulse counts while maintaining programming completeness through subsequent refinement in the second pass.

Inventive Principle:

Principle #16Partial or excessive action

Solution Approach 2:

The first pass performs preliminary programming into intermediate threshold voltage ranges before the second pass completes the programming into final ranges. This preliminary action reduces the total number of pulses needed while ensuring programming completeness through the two-stage process.

Inventive Principle:

Principle #10Preliminary action

3Measurement precision

If the number of verify operations is increased to ensure accurate reading, then the data accuracy improves, but the operation time increases

Engineering Contradiction:

Improvedata reading accuracyVSAvoidverify operation time

Core Design Contradiction:

Measurement precisionVSLoss of time

Solution Approach 1:

The patent merges and shares verify operations between different programming passes and threshold voltage ranges. By combining verify operations that would otherwise be separate, the patent maintains data reading accuracy while significantly reducing the total number of verify pulses and operation time.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The verify operations are designed to serve multiple functions across different programming passes and threshold voltage ranges. A single verify operation can validate multiple states, making the verify mechanism more universal and reducing the total number of operations required while maintaining accuracy.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS20250364052A1Program operations in memory devices

Publication Date: 2025.11.27 YANGTZE MEMORY TECH CO LTD

AI summary

Example memory devices, systems, and methods for reducing verify operation time in memory devices are disclosed. One example method includes performing, based on one of 2N pieces of N-bits data, a first programming operation of the target memory cell to program the target memory cell into an intermediate threshold voltage rangeP1Iof a first set of 2N-1 threshold voltage ranges{P10,P11,… ,P12N-2},whereP12N-2⁢ and⁢ P12N-3share a same verify voltage. A second programming operation of the target memory cell is performed, based on the one of 2N pieces of N-bits data and the intermediate threshold voltage rangeP1I,to program the target memory cell into one of a second set of 2N threshold voltage ranges{P20,P21,… ,P22N-1},where{P20,P21,… ,P22N-1}correspond to the 2N pieces of N-bits data respectively, andP10corresponds toP20⁢ and⁢ P21.