Non-Volatile Memory Programming with Adaptive Verify Skipping
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Solution Overview
Problem
As the number of bits stored per memory cell increases in non-volatile memory devices, the number of verify pulses required in each loop of the increment step pulse programming (ISPP) method also increases, leading to performance degradation and longer program times.
Innovation Solution
A method that applies a first program pulse and verify pulse in a program loop, counts off cells based on the verify pulse output, determines a verify skip period, and then applies additional program and verify pulses only when necessary, optimizing the number of pulses and reducing unnecessary verification steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of bits stored per memory cell increases, then the storage capacity increases, but the number of verify pulses required in each ISPP loop increases leading to longer program time
Solution Approach 1:
The patent implements a verify skip mechanism where verify pulses are selectively omitted in certain ISPP loops based on programming conditions. When the number of off cells is below a threshold or when programming progress indicates sufficient verification, the method skips verify pulses in subsequent loops, thereby reducing the total number of verify operations while maintaining programming reliability for high-capacity memory cells.
Solution Approach 2:
The patent dynamically adjusts the verify pulse application strategy based on real-time programming status. The verify skip period is determined adaptively according to the number of off cells and programming loop progress, allowing the system to optimize verification frequency dynamically rather than applying verify pulses uniformly across all loops, thus reducing overall program time for multi-bit memory cells.
2Manufacturing precision
If the number of verify pulses in each ISPP loop increases, then the programming accuracy improves, but the total program time increases
Solution Approach 1:
The patent selectively skips verify pulses in later ISPP loops when programming conditions indicate that continued verification would provide diminishing returns. The verify skip determination logic evaluates off cell counts and programming progress to decide when to omit verify pulses, maintaining adequate programming accuracy while significantly reducing the total number of verify operations required.
Solution Approach 2:
The patent applies verify pulses partially - not in every ISPP loop - based on the determined verify skip period. This partial verification approach is sufficient to ensure programming accuracy for multi-bit memory cells while avoiding the excessive verification that would occur if verify pulses were applied in every single loop, thus optimizing the balance between accuracy and speed.
3Reliability
If the number of off cells is high, then more verify pulses are needed to ensure proper programming, but this increases program time
Solution Approach 1:
The patent implements a feedback mechanism where the off cell count is continuously monitored and used to determine the verify skip period. When off cell counts are high, the system adjusts the verification strategy accordingly - potentially reducing the verify skip period to ensure adequate verification. This feedback-based adaptation maintains programming reliability while optimizing program time by avoiding unnecessary verify pulses when conditions permit.
Data Source
AI summary
A method of operating a memory device that performs a plurality of program loops for a plurality of memory cells includes applying a first program pulse and a first verify pulse of a first program loop from among the plurality of program loops, counting a first off cell count by using an output based on the first verify pulse, determining a first verify skip period using the first off cell count, applying an N-th program pulse and a plurality of verify pulses in response to an end of the first verify skip period, counting a second off cell count by using an output based on the plurality of verify pulses, and determining a second verify skip period using the second off cell count.