Non-Volatile Memory Programming Voltage Adjustment
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Solution Overview
Problem
Non-volatile semiconductor memory devices, such as NAND type flash memory, face challenges in reducing interference between memory cells, which leads to reduced read margins and increased errors during programming due to threshold voltage shifts caused by coupling effects, oxide layer deterioration, and programming disturbances.
Innovation Solution
A programming method that adjusts the program-verify-voltage of a selected memory cell based on the interference from adjacent cells, using a memory controller to determine and trim the verify voltage levels to minimize coupling effects, allowing for accurate programming and reduced errors by compensating for the influence of interfering cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory cells are programmed using conventional verify voltage levels, then programming speed is maintained, but interference between adjacent cells causes threshold voltage shifts and increases programming errors
Solution Approach 1:
The patent applies preliminary anti-action by adjusting the program-verify-voltage of selected memory cells based on the programming data to be written in interfering cells before the actual programming occurs. The memory controller predicts the interference effect from adjacent cells and pre-adjusts the verify voltage levels to compensate for expected threshold voltage shifts, thereby preventing programming errors before they happen.
Solution Approach 2:
The patent changes the electrical parameter (program-verify-voltage level) of the selected memory cell based on the programming state of interfering cells. The memory controller dynamically adjusts the verify voltage among multiple levels according to the data to be programmed in adjacent cells, transforming a fixed parameter system into a variable one that adapts to interference conditions.
2Reliability
If the program-verify-voltage is adjusted to compensate for interference, then programming accuracy improves, but the complexity of the programming control increases
Solution Approach 1:
The patent implements feedback by having the memory controller continuously monitor the programming state of interfering cells and use this information to adjust the program-verify-voltage for selected cells. The system creates a closed-loop control where the programming data in adjacent cells provides feedback that determines the appropriate verify voltage level, enabling dynamic adaptation to interference conditions.
Solution Approach 2:
The memory controller performs preliminary analysis of the programming data to be written in interfering cells before initiating the programming operation on selected cells. By predicting the interference effect in advance and preparing the appropriate verify voltage levels beforehand, the system reduces the complexity of real-time control while maintaining high programming accuracy.
3Device complexity
If conventional programming methods are used, then device complexity is minimized, but multi-bit errors increase due to coupling effects and oxide layer deterioration
Solution Approach 1:
The patent changes the program-verify-voltage parameter from a fixed conventional value to a dynamically adjusted value based on interference conditions. By introducing multiple verify voltage levels and selecting appropriate levels according to the programming state of interfering cells, the system reduces multi-bit errors caused by coupling effects and oxide layer deterioration without requiring fundamental changes to the device structure.
Data Source
AI summary
Provided are a non-volatile memory system and a programming method thereof. The programming method of the non-volatile memory system includes adjusting a program-verify-voltage of a selected memory cell referring to program data to be written in an interfering cell configured to provide interference for the selected memory cell and programming the selected memory cell depending on the adjusted program-verify-voltage.