Memory Programming Voltage Reduction via Negative Pillar Bias

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Current memory programming operations require high maximum programming voltage, which can lead to increased die size and manufacturing costs, while also posing challenges in maintaining data reliability and efficiency.

Innovation Solution

Applying a negative voltage to the pillar of a memory cell string during programming operations, allowing for a reduction in maximum programming voltage while maintaining the same level of programming stress, by floating the pillars of both selected and unselected sub-blocks and discharging unselected wordlines to a predefined potential.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If high maximum programming voltage is applied during memory programming operations, then programming stress and data reliability are maintained, but die size and manufacturing costs increase

Engineering Contradiction:

Improvedata reliabilityVSAvoiddie size

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent changes the voltage parameter by applying negative voltage to selected wordlines and pillar structures during programming operations. This parameter change enables the same programming stress to be achieved with lower maximum programming voltage, thereby reducing die size while maintaining data reliability.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent introduces pillar structures as intermediary elements between wordlines and memory cells. These pillars concentrate and direct the electric field, enabling effective programming stress application with reduced overall voltage requirements, thus reducing die size without compromising reliability.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If high maximum programming voltage is applied during memory programming operations, then programming stress is maintained, but manufacturing costs increase

Engineering Contradiction:

Improveprogramming stressVSAvoidmanufacturing costs

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

By changing the voltage application parameters to include negative voltage on selected wordlines and pillars, the patent achieves the required programming stress with lower maximum voltage. This reduces manufacturing complexity and costs while maintaining programming effectiveness.

Inventive Principle:

Principle #35Parameter changes

3Productivity

If high maximum programming voltage is applied during memory programming operations, then programming effectiveness is maintained, but energy efficiency per bit decreases

Engineering Contradiction:

Improveprogramming effectivenessVSAvoidenergy efficiency per bit

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent optimizes voltage parameters by applying negative voltage to selected wordlines and pillars, which concentrates the electric field more efficiently. This achieves the same programming effectiveness with lower total energy consumption, improving energy efficiency per bit.

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces the maximum programming voltage, resulting in improved die size and energy efficiency per bit, while maintaining data reliability and reducing manufacturing costs.

Implementation Method 1

Methodology Applied

Scientific EffectElectric Field: Electric Field

Data Source

PatentUS11742036B2Reducing maximum programming voltage in memory programming operations

Publication Date: 2023.08.29 MICRON TECHNOLOGY INC

AI summary

Described are systems and methods for reducing maximum programming voltage in memory programming operations. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines; and a controller coupled to the memory array, the controller to perform operations comprising: identifying one or more memory cells for performing a memory programming operation, wherein the memory cells are electrically coupled to a target wordline and one or more target bitlines; causing drain-side select gates and source-side select gates of the memory array to be turned off; causing unselected wordlines of the memory array to discharge to a predefined voltage level; and causing one or more programming voltage pulses to be applied to the target wordline.