Memory Protection via Address Transformation and Frequency Monitoring
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Solution Overview
Problem
Modern memory devices, particularly DDR memories, are vulnerable to Row Hammer attacks, which cause data corruption by repeatedly accessing a single row of memory, leading to unauthorized access and data leakage, with existing solutions like ECC and PARA being costly and performance-intensive.
Innovation Solution
A memory device with a protection system that includes a transformation unit to transform addresses based on access frequency, using a balanced and non-injective function, and an access frequency manager to trigger memory protection operations, along with an optional scrambler to scramble address bits, preventing excessive access and making Row Hammer attacks difficult to exploit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ECC (Error Correcting Codes) is used to protect against Row Hammer attacks, then memory reliability is improved, but memory capacity is reduced and cost increases
Solution Approach 1:
The patent divides the address space into multiple segments using a hash function that maps the original address to a segment identifier. By tracking access frequency per segment rather than per individual address, the system achieves Row Hammer protection without requiring ECC bits for every memory location, thus preserving usable capacity while maintaining reliability.
2Reliability
If frequent refresh of all rows is implemented, then memory reliability is improved, but performance deteriorates due to access delays
Solution Approach 1:
The patent implements a dynamic refresh strategy where the refresh frequency is adjusted based on detected access patterns. When Row Hammer attacks are detected through address transformation analysis, the system increases refresh frequency for affected segments. During normal operation, standard refresh timing is maintained, thus preserving performance while ensuring reliability when needed.
Solution Approach 2:
The system continuously monitors memory access patterns through address transformation and hashing. When excessive access to specific address segments is detected, the system provides feedback by triggering targeted refresh operations for those segments. This closed-loop approach ensures reliability through timely refresh while maintaining high performance during normal operation by avoiding unnecessary refreshes.
3Reliability
If PARA (Probabilistic Adjacent Row Activation) is used, then memory reliability is improved, but performance overhead increases due to unnecessary refreshes
Solution Approach 1:
The patent applies address transformation and hashing before memory access operations to identify potentially vulnerable address segments in advance. By pre-processing addresses through the hash function and tracking segment access patterns, the system can proactively detect Row Hammer attacks and trigger refresh operations before data corruption occurs, rather than relying on probabilistic refresh of adjacent rows. This eliminates unnecessary refreshes while maintaining protection.
4Reliability
If address transformation with hashing is implemented, then security against Row Hammer attacks is improved, but device complexity increases
Solution Approach 1:
The patent implements a virtual address transformation layer that creates a hashed representation of physical addresses. Instead of modifying the physical memory structure or adding complex protection circuitry, the system uses software-based address hashing and segment tracking to provide Row Hammer protection. This virtualization approach maintains security while avoiding significant increases in hardware complexity.
Data Source
AI summary
Embodiments provide a memory device including a memory comprising at least one chip, each chip comprising one or more banks for storing a plurality of bits, each bank comprising a set of rows and columns, each row and column comprising a number of bits, the device further comprising a controller configured to generate access commands to the memory, an access command identifying an address corresponding to a given row of the memory and a command operation to be performed on the given row, wherein the device further comprises a protection device. The protection device is configured to transform an address, in response to the receipt of an access command identifying the address, into a transformed address. The protection device uses an address storage data structure, such as a histogram, to store the transformed address depending on a frequency of access associated with the address, the address storage data structure being reset in response to a memory protection operation (refresh for example) performed in the memory device. The protection device further comprises an access frequency manager configured to determine whether the access frequency associated with an address maintained in the address storage data structure is greater or equal to a threshold, and if so trigger a memory protection operation in the memory from within the memory.