Memory Protection via Dynamic Address Translation Remapping
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory protection methods, such as encrypting data and scrambling physical addresses, are susceptible to information leakage due to detectable data reuse over extended periods, which compromises security.
Innovation Solution
An apparatus and method that utilize address translation circuitry to transition between a first and second translation function for logical and physical addresses, with a remapping array to control access, allowing for seamless remapping of memory locations without disrupting normal data processing operations by maintaining transitional data and performing remapping in single address steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is stored in encrypted form or physical addresses are scrambled to protect memory, then security is improved, but information leakage occurs over extended periods due to detectable data reuse
Solution Approach 1:
The patent implements dynamic address translation by switching between multiple translation functions (first and second translation functions) based on remapping array entries. This dynamic switching prevents predictable address patterns and eliminates detectable data reuse, resolving the contradiction between memory protection and information leakage prevention.
Solution Approach 2:
The system changes the translation parameters by alternating between different translation functions. The remapping array controls which translation function is applied to each memory location, effectively changing the address mapping parameters over time to prevent information leakage while maintaining security.
2Reliability
If multiple translation functions are implemented to prevent information leakage, then security is improved, but device complexity increases
Solution Approach 1:
The address translation circuitry is designed with multi-functionality, capable of performing both the first and second translation functions using the same hardware resources. The remapping array directs which function to use, eliminating the need for separate dedicated circuits for each translation function and thus reducing overall device complexity.
Solution Approach 2:
The remapping array serves as an intermediary that controls the selection between translation functions. This intermediary structure simplifies the system by providing a straightforward control mechanism that determines which translation function is applied, avoiding the need for complex control logic in the translation circuitry itself.
3Reliability
If address remapping is performed to switch between translation functions, then security is improved, but disruption to data processing operations occurs
Solution Approach 1:
The system performs preliminary actions by pre-computing and storing remapping information in the remapping array before actual data processing occurs. This allows the address translation to switch between functions without disrupting ongoing operations, as the remapping decisions are already prepared in advance.
Solution Approach 2:
The address translation circuitry maintains continuous operation by seamlessly switching between translation functions without interrupting data processing. The remapping array enables this continuity by providing pre-determined translation decisions, ensuring that memory protection operations do not disrupt productive data processing activities.
Data Source
AI summary
Apparatus, methods, and software for protecting a plurality of memory locations are disclosed. Logical addresses are translated into physical addresses in dependence on one of a first translation function and a second translation function. A transitional logical address and an associated transitional value are locally held in circuitry which applies the translation functions. A remapping of first to second translation function usage is performed by determining a new transitional physical address by applying the second translation function to the transitional logical address; determining a new transitional logical address by applying an inverse of the first translation function to the new transitional physical address; retrieving a new transitional value using the new transitional physical address; storing the old transitional value to the memory location indicated by the new transitional physical address; and locally storing the new transitional value. This remapping can be interleaved with normal memory accesses.