Memory Protection Cache for Secure Peer-to-Peer Access
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Solution Overview
Problem
Current memory management systems in computer systems face bottlenecks and increased latency due to the need for host-reflected/bounced memory requests for memory protection checks, especially in disaggregated cloud platforms.
Innovation Solution
Implementing a distributed secure address translation service (ATS) architecture with a memory protection cache (MPC) closer to device memory, allowing for secure direct peer-to-peer memory access without host intervention, and synchronizing MPC information with a host's memory protection unit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If host-reflected memory requests are used for memory protection checks, then security is maintained, but latency increases and performance deteriorates
Solution Approach 1:
The patent introduces a Memory Protection Cache (MPC) as an intermediary component between devices and the host memory protection unit. The MPC stores memory protection information locally at the device level, enabling direct peer-to-peer memory access without requiring host reflection. This intermediary structure allows devices to perform protection checks independently, eliminating the latency associated with host-reflected requests while maintaining security through localized protection information.
2Reliability
If host-reflected memory requests are used for memory protection checks, then security is maintained, but device complexity increases
Solution Approach 1:
The patent extracts the memory protection function from the centralized host and places it at the device level through the Memory Protection Cache. By taking out the protection check capability from the host-reflection path and embedding it directly in devices, the system eliminates the need for complex host-mediated access paths. Devices can independently manage their own memory protection, simplifying the overall access architecture while maintaining robust security.
3Productivity
If direct peer-to-peer memory access is enabled, then performance improves, but security control is weakened
Solution Approach 1:
The patent enables devices to perform memory protection checks independently through locally stored Memory Protection Cache information. Each device serves its own security needs by using cached protection data to validate peer-to-peer access requests without requiring host intervention. This self-service approach allows high-performance direct memory access while maintaining security control, as devices autonomously verify access rights using pre-loaded protection information.
Data Source
AI summary
An embodiment of an integrated circuit comprises circuitry to store memory protection information for a non-host memory in a memory protection cache, and perform one or more memory protection checks on a translated access request for the non-host memory based on the stored memory protection information. Other embodiments are disclosed and claimed.