Memory Protection Device Using Latch Circuitry for Kill Signal Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory protection techniques are vulnerable to power analysis attacks, require significant resources, and are either slow or large in size, failing to effectively secure data against unauthorized access, especially in mobile contexts where power consumption and detection are concerns.
Innovation Solution
A memory protection device utilizing latch circuitry to control a memory status value, disabling access through a memory kill signal that can only be reset with a power reboot, combined with disabling circuitry to ensure enable signals are only provided in a disabled state, thereby preventing access and masking operational details from hackers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If full erase process is used to protect memory data, then data security is improved, but power consumption increases and the process takes a long time
Solution Approach 1:
The patent extracts the essential security function from the full memory erase process. Instead of erasing the entire memory content, it uses a latch circuit to store a protection status and a kill signal to disable access to the memory region. This extraction approach maintains security while eliminating the need for power-intensive full erase operations.
Solution Approach 2:
The patent changes the state parameter of memory access from 'fully erased' to 'access disabled'. By using the latch circuit to hold a memory status value and the kill signal to control access, the system transitions from a time-consuming erase process to a rapid state change mechanism that achieves equivalent security protection with minimal power consumption.
2Reliability
If full erase process is used to protect memory data, then data security is improved, but the process takes a long time
Solution Approach 1:
The patent extracts the security function from the time-consuming full erase process. By using a latch circuit to store protection status and a kill signal to disable access, the system achieves security protection without requiring the lengthy erase operation, thus reducing the time loss while maintaining data security.
3Reliability
If masking function is used to block data readout, then data access control is improved, but vulnerability to power analysis attacks remains
Solution Approach 1:
The patent applies preliminary anti-action by disabling the enable signal before any read or write operation can occur. The latch circuit holds the memory status in a disabled state, and the kill signal prevents the enable signal from being generated in the first place. This preliminary prevention eliminates the opportunity for power analysis attacks to observe read operations, as the memory remains inaccessible from the outset.
Solution Approach 2:
The patent introduces an intermediary mechanism - the latch circuit with memory status value and the kill signal - that stands between the external controller and the memory. This intermediary blocks all access attempts including power analysis observations, while still allowing normal operation when properly authorized. The intermediary prevents direct observation of memory operations from external attackers.
4Reliability
If existing memory protection techniques are used, then data protection is achieved, but device complexity or area requirement increases
Solution Approach 1:
The patent makes the latch circuit multi-functional, having it serve both as a status holder and as part of the control mechanism. The same latch circuit that holds the memory status value also interacts with the kill signal to enable/disable access. This multi-functionality reduces the need for separate dedicated circuits, thereby reducing overall device complexity while maintaining data protection capabilities.
Data Source
AI summary
A memory protection device for controlling access to a memory and a method of controlling access to a memory are disclosed. A memory status value held by latch circuitry in the memory protection device determines whether the memory is an enabled or a disabled state. After power-up, a power-on-reset signal causes the memory status value to indicate the enabled state. In response to the assertion from a received control signal a memory kill signal is generated by the memory protection device which causes the memory status value to switch to its disabled state and the memory status value then cannot be changed back to the enabled state without a power reset. The memory status value being in the disabled state causes enable signal generation circuitry of the memory to openly be able to generate its read enable signal and write enable signal in a disabled state, thus preventing access to the memory.