Memory Protection Shim for CPU Instruction Authentication
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Solution Overview
Problem
Current computing architectures are inadequate in addressing memory corruption vulnerabilities and cyber-attacks on industrial control systems, as they fail to distinguish between program instructions and data, leading to potential code injection, data theft, and system damage.
Innovation Solution
A memory protection shim is integrated with the CPU core to perform authentication and decryption of digital blocks, preventing external modifications and ensuring that only trustworthy instructions and data are consumed by the CPU, thereby enforcing a security boundary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If von Neumann architecture is used to store program instructions and data in the same memory, then memory utilization is improved, but security against memory corruption vulnerabilities deteriorates
Solution Approach 1:
The patent segments the previously unified memory space into distinct instruction memory and data memory regions. This segmentation allows the system to maintain efficient memory utilization while providing separate security boundaries that prevent memory corruption vulnerabilities from affecting both instruction and data spaces equally.
Solution Approach 2:
The patent applies different security characteristics to different memory regions. Instruction memory receives enhanced protection mechanisms including authentication and encryption, while data memory has its own security controls. This local differentiation of security quality allows the system to protect critical instruction code while maintaining efficient data access patterns.
2Reliability
If traditional perimeter defense and firewall mechanisms are used, then network security is improved, but protection against embedded system vulnerabilities deteriorates
Solution Approach 1:
The patent introduces a memory protection shim as an intermediary layer between the CPU core and the memory system. This shim provides authentication, encryption, and decryption functions that protect embedded systems from memory corruption vulnerabilities, complementing traditional network-level security measures with hardware-enforced memory protection.
Solution Approach 2:
The patent implements security checks and transformations on data before it reaches the CPU core. By performing authentication and decryption operations in advance through the memory protection shim, the system prevents malicious code or corrupted data from entering the execution pipeline, addressing embedded system vulnerabilities proactively rather than reactively.
3Quantity of substance
If memory stores program instructions and data without differentiation, then storage efficiency is improved, but susceptibility to code injection attacks deteriorates
Solution Approach 1:
The patent divides the unified memory space into separate instruction and data segments. This segmentation maintains storage efficiency by allowing both types of content to reside in the same physical memory infrastructure, while simultaneously preventing code injection attacks by establishing clear boundaries that prevent data from being misinterpreted as executable instructions.
Solution Approach 2:
The patent applies different security attributes to instruction memory versus data memory. Instruction memory regions are configured with authentication requirements and execution permissions that prevent code injection, while data memory regions maintain efficient storage and access characteristics appropriate for non-executable content.
Data Source
AI summary
An apparatus comprising a CPU core configured to execute instructions and consume data. The apparatus includes a memory configured to store the instructions and the data. A memory protection shim is coupled to the CPU core and the memory. The memory protection shim is configured to perform transformations over digital blocks to perform at least one of authentication or decryption of the digital blocks received from the memory. The memory protection shim is coupled to the CPU core in a fashion that prevents egress of the digital blocks or ingress of other external digital blocks between the memory protection shim and the CPU core.