Memory Protection Unit for Secure Instruction Data Access
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In secure systems like Pay-TV decoders, existing technologies face challenges in ensuring the authenticity of code executed by microprocessors, as they may run unauthorized code, compromising security and revenue protection for code providers.
Innovation Solution
A hardware mechanism within the microprocessor enforces associations between instructions and data using a memory protection unit, which prevents execution of unauthorized code by comparing instruction addresses with valid ranges stored in a secure memory, ensuring only trusted code can access secure data regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a microprocessor executes code from physical memory without hardware enforcement, then the system operates with flexibility and ease of operation, but the security and reliability are compromised as unauthorized code may be executed
Solution Approach 1:
The system performs preliminary validation by storing valid instruction address ranges in a secure memory region before code execution. The memory protection unit checks whether instruction addresses fall within these pre-defined valid ranges during execution, preventing unauthorized code from being run without requiring complex runtime verification mechanisms.
Solution Approach 2:
A memory protection unit is introduced as an intermediary component between the microprocessor and physical memory. This unit intercepts memory access requests, validates instruction addresses against the secure memory region, and blocks unauthorized accesses. It acts as a mediator that enforces security rules without requiring changes to the core processor architecture.
2Reliability
If applications can access any memory region, then the ease of operation and adaptability are improved, but the security is worsened as hacking and data corruption become possible
Solution Approach 1:
The system applies different access permissions to different memory regions. The secure memory region contains valid instruction address ranges with restricted access, while other memory regions maintain their traditional access patterns. This localized security approach protects critical areas without imposing blanket restrictions that would reduce overall system adaptability.
Solution Approach 2:
The memory space is segmented into secure and non-secure regions. The secure memory region stores validated instruction address ranges, while the main physical memory contains executable code and data. This segmentation allows the system to enforce strict access control where needed while maintaining flexibility in other areas.
3Reliability
If code validation is performed by software only, then the device complexity is reduced, but the security is insufficient as unauthorized code can bypass software checks
Solution Approach 1:
The system replaces software-based code validation with a hardware enforcement mechanism. The memory protection unit, implemented in hardware, automatically validates instruction addresses against the secure memory region without requiring software intervention. This hardware enforcement provides stronger security guarantees while maintaining relatively simple system architecture.
Data Source
AI summary
A semiconductor integrated circuit includes a hardware mechanism arranged to ensure that associations between instructions and data are enforced so that a processor cannot fetch data from an instruction that is not authorized to do so. A Memory Protection Unit stores entries comprising instructions and associated data memory ranges. A hardware arrangement impairs the operation of the circuit if the processor attempts to make a data fetch from an instruction that is outside the range associated with data in a Memory Protection Unit. Such functioning may be by issuing a chip reset. The Memory Protection Unit may be implemented in a Memory Management Unit having an extension so as to store a validity flag. The validity flag may only be set by a secure process such as the CPU well entrusted code or by a separate trusted hardware source.