Memory Protection Unit Mask-Based Region Identification

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Solution Overview

Problem

Existing data processing systems face inefficiencies in memory management, particularly in associating attributes with memory addresses and managing memory regions, leading to slow comparisons and high energy consumption.

Innovation Solution

The implementation of a memory protection unit that divides the memory address space into programmable regions with a mask-based comparison system to rapidly identify memory blocks and associate attributes, alongside a memory management unit using hierarchical page table data for efficient memory access.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If traditional memory management units use conventional comparison methods to determine memory attributes, then the system can provide memory protection and attribute association, but the comparison process consumes excessive energy and operates slowly

Engineering Contradiction:
Improveenergy consumptionVSAvoidmemory access speed
Core Design Contradiction:
Use of energy by moving objectVSProductivity

Solution Approach 1:

The patent segments the memory address space into distinct memory regions with programmable boundaries. Each region can have independent attributes (read-only, cacheability, privilege levels). This segmentation allows the comparison logic to operate on region-level identifiers rather than individual addresses, reducing computational complexity and energy consumption while maintaining fast access speeds.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system pre-establishes memory regions with their boundaries and attributes before memory access operations occur. The memory protection unit is configured with region definitions in advance, allowing it to quickly determine attributes for any address within those pre-defined regions without performing complex real-time comparisons.

Inventive Principle:
Principle #10Preliminary action

2Adaptability or versatility

If memory address space is divided into multiple memory regions with programmable boundaries, then attribute association capability is improved, but the complexity of managing and comparing regions increases

Engineering Contradiction:
Improveattribute association capabilityVSAvoidregion management complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent introduces a memory protection unit as an intermediary component between the memory management unit and the memory system. This intermediary handles the complexity of region management, boundary checking, and attribute determination, shielding the main processor from these complexities while providing versatile attribute association capabilities through programmable region definitions.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If conventional memory management methods are used without mask-based comparison, then the system can provide basic memory protection, but the comparison operations are slow and energy-intensive

Engineering Contradiction:
Improvememory protection accuracyVSAvoidcomparison operation time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent replaces conventional sequential comparison methods with a mask-based comparison mechanism. Instead of sequentially checking address boundaries and calculating overlaps, the system uses bit masking operations to simultaneously evaluate multiple region conditions, dramatically reducing comparison time and energy consumption while maintaining accurate memory protection.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentEP3029574B1Memory management
Publication Date: 2019.09.18 ARM LTD
  • EP3029574B1 patent drawingFigure 1
  • EP3029574B1 patent drawingFigure 2
  • EP3029574B1 patent drawingFigure 3

AI summary

Memory management is provided within a data processing system 2 which includes a memory protection unit 8 and defines memory regions within the memory address space which extend between base addresses and limit addresses and have respective attributes associated therewith. When a hit occurs within a memory region which is a valid hit, then block data is generated comprising a mask value and a TAG value (derived from the original query address) which may then be used to identify subsequent hits within at least a portion of that region using a bitwise AND. In another embodiment a micro-translation lookaside buffer is reused by the memory protection unit to store page data identifying pages which fall validly within memory regions and may be used to return attribute data for those pages upon subsequent accesses rather than performing the comparison with the base address and the limit addresses.