Memory System Point-to-Two-Point Link Signal Merging
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Solution Overview
Problem
Conventional memory systems face challenges in reducing capacitive loading on signal lines, particularly at high speeds, which affects operation speed and complexity in designing high-density memory modules with point-to-point links, and thermal management issues arise with stacked memories.
Innovation Solution
Implementing a memory system with point-to-two-point links for merged write and command/address signals and point-to-point links for read data signals, using flexible conductor elements and connectors to connect memory modules without increasing the number of connector pins, allowing for efficient signal transmission and thermal management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If point-to-point links are used between memory devices to reduce capacitive loading, then operation speed is improved, but the number of connector pins and module tabs increases, making design and production difficult
Solution Approach 1:
The patent merges the command/address signal lines and write data signal lines into a single shared link, allowing both signal types to be transmitted simultaneously through the same physical connection. This reduces the number of separate connector pins required while maintaining point-to-point connectivity for high-speed operation.
Solution Approach 2:
The shared link serves multiple functions by carrying both command/address signals and write data signals. The controller can identify the signal type and route appropriate data to the correct memory device, enabling a single physical connection to perform what would traditionally require multiple dedicated connections.
2Quantity of substance
If stacked memories are used on a single memory module to support PTP links, then memory density is increased, but thermal management becomes difficult and signal routing becomes complex
Solution Approach 1:
The patent divides the memory system into multiple memory modules, each containing a subset of memory devices. This segmentation allows for simpler signal routing within each module while distributing thermal loads across multiple modules, avoiding the complexity of routing signals through stacked configurations.
Solution Approach 2:
Instead of stacking memories vertically (adding a third dimension), the patent organizes memory devices in planar arrays across multiple modules. This dimensional approach simplifies signal routing by keeping connections primarily within the same plane and reduces thermal management complexity by distributing heat across a larger area.
3Device complexity
If multiple memory devices share common C/A signal lines, then device complexity is reduced, but capacitive loading increases, degrading operation speed
Solution Approach 1:
The patent combines command/address signals and write data signals into a single shared link that connects multiple memory devices. This merging reduces the number of separate signal lines required while maintaining high-speed operation by avoiding the capacitive loading that would result from having separate C/A lines for each device.
Data Source
AI summary
A memory system has first and second primary memories and first and second secondary memories coupled to the first and second primary memories, respectively, the coupling comprising at least one point-to-point connection. A memory module includes at least two of the first and second primary and first and second secondary memories. A first connection element, such as a connector or solder, connects the memory module to a mother board. A second connection element, such as a connector or solder, connects at least one other of the first and second primary and first and second secondary memories to the mother board. At least one of the memories on the first memory module is coupled to at least one of the other memories. The memory system also includes a memory controller which is connected to the primary memories by a point-to-two-point link.