Semiconductor Memory PUF Using Capacitor Breakdown Signatures
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Solution Overview
Problem
There is a need for secure and cost-effective methods to protect sensitive information stored in electronic devices, particularly in integrated circuits, without relying on expensive hardware like EEPROMs, by leveraging manufacturing variability to create unique authentication signatures.
Innovation Solution
A physically unclonable function (PUF) memory device is developed using a memory array with pairs of capacitors, where the breakdown of capacitors under programming voltage generates unique logic states, forming a PUF signature, and this system is integrated with existing CMOS processing technologies for high-density, tamper-resistant authentication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If expensive hardware like EEPROM is used to store authentication data, then security and reliability are improved, but device cost increases
Solution Approach 1:
The patent replaces expensive EEPROM hardware with a cost-effective PUF-based authentication system that utilizes inherent manufacturing variability in standard memory cells. The PUF signature is generated from physical characteristics of capacitors and transistors that naturally vary during manufacturing, eliminating the need for additional secure storage hardware while maintaining authentication security.
Solution Approach 2:
The system leverages the natural manufacturing variability and physical characteristics of the memory device itself to generate unique authentication signatures. Each device's PUF signature is inherently embedded in its physical structure through capacitor breakdown patterns and transistor threshold variations, requiring no external programming or configuration hardware.
2Device complexity
If PUF signature generation is integrated into existing CMOS processing, then manufacturing complexity is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent converts the harmful effect of manufacturing variability, which traditionally degrades device performance, into a beneficial feature for authentication. The inherent variations in capacitor breakdown voltages and transistor threshold voltages, which are normally considered defects, are harnessed to create unique PUF signatures that provide secure device identification and authentication.
Solution Approach 2:
The system changes the operational parameters of memory cells by applying high programming voltages that induce controlled breakdown in capacitor dielectric layers. This breakdown process creates irreversible physical changes that form the basis of the PUF signature, transforming standard memory cells into authentication elements without requiring separate manufacturing processes.
3Reliability
If capacitor breakdown is used to generate PUF signatures, then unique authentication is achieved, but manufacturing variability must be controlled
Solution Approach 1:
Instead of trying to minimize manufacturing variability to achieve consistent device performance, the patent inverts the approach by deliberately exploiting variability to create unique authentication signatures. The PUF system is designed to capture and utilize the natural differences between devices rather than eliminate them, turning a manufacturing challenge into a security advantage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a secure, cost-effective means to generate unique PUF signatures for each memory device, enhancing authentication and preventing unauthorized access by utilizing manufacturing variability, thus ensuring secure storage and communication without the need for expensive hardware.
Implementation Method 1
the breakdown of capacitors under programming voltage generates unique logic states, forming a PUF signature
Data Source
AI summary
A method for fabricating memory devices includes: forming a gate dielectric layer; forming a first semiconductor film on a first side of the gate dielectric layer; forming a first metal structure on a second side of the gate dielectric layer opposite to the first side, the first metal structure extending along a first lateral direction; forming a first conductive structure on the second side over the first semiconductor film, the first conductive structure extending along the first lateral direction to traverse across the first semiconductor film, and further extending along a vertical direction; forming a second conductive structure on the second side over the first semiconductor film, wherein the second conductive structure extends along the vertical direction; and forming a third conductive structure on the second side over the first semiconductor film, the third conductive structure extending along the vertical direction.