Non-Volatile Memory PUF Layout for Stable Threshold-Based Codes

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Solution Overview

Problem

Existing physical unclonable functions (PUFs) within integrated circuits are not robust enough to withstand temperature variations and aging, are sensitive to attacks, and have a large surface footprint, making them difficult to produce and secure.

Innovation Solution

A PUF device comprising non-volatile memory cells with depletion-type state transistors and a processing circuit that generates a unique, unpredictable code by reading the effective threshold voltages of these transistors, organized in symmetric matrix sub-assemblies to enhance dispersion and reliability, with a second assembly for reliability information storage, and a method for generating and storing reliability information.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional PUF structures are used, then the device can generate unique codes, but the device is not robust enough to withstand temperature variations and aging

Engineering Contradiction:
Improverobustness to temperature variations and agingVSAvoidmanufacturing complexity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent changes the operating parameters of the memory cells by using depletion-type state transistors with control gates that can be biased at different voltages. This allows the PUF to operate reliably across temperature variations and aging effects by adjusting the threshold voltage parameters of the transistors, thereby improving robustness without requiring fundamental manufacturing changes

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent implements redundancy mechanisms and error correction codes beforehand to cushion against potential failures due to temperature variations and aging. By preparing backup pathways and correction mechanisms in advance, the system maintains reliability over time without requiring complex real-time adjustments

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

2Reliability

If conventional PUF structures are used, then the device can generate unique codes, but the device has a large surface footprint

Engineering Contradiction:
Improvecode uniqueness and predictabilityVSAvoidsurface footprint
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges the PUF functionality with existing non-volatile memory cell structures that already have depletion-type state transistors. By combining the unique code generation function with the memory storage function in a single integrated structure, the patent achieves code uniqueness while significantly reducing the surface footprint compared to dedicated PUF circuits

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent makes the memory cells serve multiple functions: they act as both storage elements and PUF elements for generating unique codes. This multi-functionality allows the same hardware structure to provide both data storage and security functions, eliminating the need for separate PUF circuitry and thereby reducing the overall surface footprint

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If conventional PUF structures are used, then the device can generate unique codes, but the device is sensitive to attacks by fault injection

Engineering Contradiction:
Improvesecurity against fault injection attacksVSAvoidstructural complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent exploits the asymmetric electrical characteristics of depletion-type state transistors, where the control gate voltage has a dominant effect on the threshold voltage. This asymmetry creates unique, unpredictable code patterns that are inherently resistant to fault injection attacks, as small perturbations cannot easily predict or replicate the output codes without knowing the exact transistor characteristics

Inventive Principle:
Principle #4Asymmetry

4Measurement precision

If conventional PUF structures are used, then the device can generate unique codes, but the data cannot be clearly discriminated on reading

Engineering Contradiction:
Improvedata discrimination capabilityVSAvoidmanufacturing simplicity
Core Design Contradiction:
Measurement precisionVSEase of manufacture

Solution Approach 1:

The patent applies local quality enhancement by using depletion-type state transistors with control gates that can be individually biased. This allows each memory cell to have optimized electrical characteristics for clear signal discrimination during reading, improving measurement precision while maintaining compatibility with standard manufacturing processes

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution provides a robust, secure, and compact PUF device that is resistant to temperature changes and attacks, with a reduced surface footprint, and easy to produce using existing technologies, while ensuring reliable data discrimination and protection against intrusive analyses.

Implementation Method 1

the state transistors of the memory cells of the first assembly are of the depletion type and have a control gate and a floating gate that are electrically connected

Methodology Applied
Scientific EffectDepletion effect:

Implementation Method 2

a control gate and a floating gate that are electrically connected

Methodology Applied
Scientific EffectElectrical connection: Conduction (electrical)

Data Source

PatentUS12001593B2Physical unclonable function device and method
Publication Date: 2024.06.04 STMICROELECTRONICS (ROUSSET) SAS
  • US12001593B2 patent drawing
  • US12001593B2 patent drawing
  • US12001593B2 patent drawing

AI summary

An embodiment system comprises a physical unclonable function device, wherein the device comprises a first assembly of non-volatile memory cells each having a selection transistor embedded in a semiconductor substrate and a depletion-type state transistor having a control gate and a floating gate that are electrically connected, the state transistors having respective effective threshold voltages belonging to a common random distribution, and a processing circuit configured to deliver, to an output interface of the device, a group of output data based on a reading of the effective threshold voltages of the state transistors of the memory cells of the first assembly.