Nonvolatile Memory Pulse Programming for Oxide Degradation
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Solution Overview
Problem
Conventional NAND cell type EEPROMs face inefficiencies in data programming and erasure operations due to narrow program voltage margins, leading to slower programming speeds and reduced reliability, as the electrical field applied to the insulation layer becomes stronger, potentially causing tunnel oxide film degradation.
Innovation Solution
A nonvolatile semiconductor memory device employs a pulse signal generation method with gradually increasing high voltages and verification mechanisms to control memory cell thresholds, using a circuit that generates first and second clock signals with different amplitudes to apply pulse signals, thereby preventing a precipitous electrical field and optimizing data programming time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional data program operation is used with fixed high voltage, then programming can be completed, but the electrical field becomes too strong causing tunnel oxide film degradation and reducing reliability
Solution Approach 1:
The patent applies periodic action by using multiple program pulses with gradually increasing voltages instead of a single fixed high voltage. The voltage is incremented in steps (e.g., Vpp0, Vpp1, Vpp2) across different pulse cycles, allowing the tunneling process to occur in controlled intervals rather than continuously at maximum stress, thus preventing oxide film degradation while achieving reliable programming.
Solution Approach 2:
The patent changes the voltage parameter dynamically during the programming process. Instead of maintaining a constant high voltage that degrades the oxide, the voltage is progressively increased from Vpp0 to Vpp1 to Vpp2 across different pulse sequences. This parameter change allows the electrical field to remain below degradation thresholds during early stages while achieving sufficient tunneling in later stages.
2Productivity
If higher voltage is applied to increase programming speed, then data programming time is reduced, but the program voltage margin becomes narrower and reliability decreases
Solution Approach 1:
The patent uses periodic program pulses with gradually increasing voltages (Vpp0, Vpp1, Vpp2) rather than applying maximum voltage continuously. This periodic approach with voltage increments maintains adequate voltage margins during early pulses while achieving fast programming through higher voltages in later pulses, thus resolving the contradiction between speed and reliability.
Solution Approach 2:
The patent applies preliminary low-voltage pulses (Vpp0, Vpp1) before applying higher voltage pulses (Vpp2). This preliminary action prepares the memory cell by initiating the tunneling process at lower stress levels, then accelerates programming with higher voltages in subsequent pulses, maintaining voltage margins while improving overall programming speed.
3Device complexity
If single high voltage pulse is used for programming, then programming operation is simple, but the electrical field causes precipitous tunneling and oxide film degradation
Solution Approach 1:
The patent segments the single high-voltage programming operation into multiple pulses with progressively increasing voltages (Vpp0, Vpp1, Vpp2). Each pulse sequence applies a controlled voltage increment, preventing the precipitous tunneling that would occur with a single abrupt high-voltage application. This segmentation maintains operational simplicity while eliminating the harmful electrical field effects.
4Loss of time
If voltage is increased to reduce programming time, then data programming time decreases, but overshoot and ripple increase affecting precision
Solution Approach 1:
The patent employs periodic pulses with controlled voltage increments (Vpp0, Vpp1, Vpp2) rather than a single high-voltage pulse. This periodic structure with gradual voltage increases reduces overshoot and ripple effects compared to abrupt high-voltage application, while still achieving reduced programming time through the cumulative effect of multiple high-voltage pulses.
Solution Approach 2:
The patent changes the voltage parameter in controlled increments (from Vpp0 to Vpp1 to Vpp2) across multiple pulses. This gradual parameter change prevents the voltage overshoot and ripple that would occur with sudden high-voltage application, maintaining precision while reducing overall programming time through the accelerated later stages.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces data programming time by up to 20% and improves memory device reliability by controlling the degradation of the tunnel oxide film and preventing breaks in insulation, while maintaining constant arrival times and minimizing overshoot and ripple.
Implementation Method 1
a charge pump circuit which generates a program pulse having a program voltage Vpp based on the clock signal PMPCLK
Implementation Method 2
a limiter circuit which limits an amplitude of the program pulse to a predetermined value
Data Source
AI summary
A nonvolatile semiconductor memory device includes a plurality of electronically reprogrammable memory cells, a circuit for applying a plurality of pulse signals having corresponding high level potentials increasing step by step to said memory cell, and verify circuit for detecting a threshold value of said memory cell after applying said plurality of pulse signals. Further, the circuit for applying said plurality of pulse signals includes a first circuit for generating a first clock having a first amplitude voltage and a second clock having a second amplitude voltage which is higher than said first amplitude voltage, a second circuit for generating said plurality of said pulse signal having corresponding predetermined voltages based on said first clock or said second clock input from said first circuit respectively, and a third circuit for stopping an input of said first clock and said second clock to said second circuit when said plurality of pulse signals generated by said second circuit reach said corresponding predetermined voltages respectively.