Memory Programming Pulse Tailoring for Select Device Retention
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Solution Overview
Problem
Existing memory device programming procedures do not adequately account for the memory effects and retention characteristics of select devices (SDs) in phase change memory and single amorphous chalcogenide memory, leading to increased errors and reduced lifespan due to suboptimal current magnitude and duration settings based on polarity of access, number of prior write cycles, and decoder distance.
Innovation Solution
Tailoring the current magnitude and duration of programming pulses during multi-stage or square programming procedures based on the polarity of access, number of prior write cycles, and decoder distance to optimize the memory effects and retention characteristics of select devices, ensuring only desired memory cells are selected and programmed effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fixed current magnitude and duration are used during programming pulses, then the programming procedure is simple, but errors increase and lifespan decreases due to suboptimal settings for select devices
Solution Approach 1:
The patent applies dynamics by transitioning from fixed programming pulse parameters to dynamic, variable parameters. The current magnitude and duration of programming pulses are adjusted based on the state of select devices (SDs), including polarity of access, number of prior write cycles, and decoder distance. This enables the programming procedure to adapt to changing conditions and optimize performance while reducing errors and extending lifespan.
Solution Approach 2:
The patent implements parameter changes by modifying current magnitude and duration based on specific conditions. Different programming pulses are applied with tailored parameters depending on the polarity of access (positive or negative), the number of prior write cycles experienced by the SD, and the decoder distance. This allows precise control over the programming process to prevent harmful effects on select devices.
2Manufacturing precision
If higher current magnitude is applied to ensure programming, then programming effectiveness improves, but harmful effects on select devices increase leading to reduced lifespan
Solution Approach 1:
The patent applies local quality by tailoring programming pulse characteristics to specific local conditions of select devices. Instead of applying uniform high current to all cells, the current magnitude and duration are localized and adjusted based on individual SD states such as polarity of access, prior write cycles, and decoder distance. This ensures sufficient programming effectiveness for each cell while minimizing harmful effects specific to its condition.
Solution Approach 2:
The patent uses partial action by applying programming pulses with current magnitude and duration precisely matched to the specific needs of each select device condition. Rather than consistently applying excessive current to ensure programming, the method applies just the right amount of current based on the SD state, avoiding unnecessary harmful effects while maintaining programming effectiveness.
3Reliability
If programming pulses are optimized for memory cells, then memory cell performance improves, but select device retention characteristics deteriorate
Solution Approach 1:
The patent resolves this contradiction through dynamics by making programming pulse parameters dependent on select device state. The system dynamically adjusts current magnitude and duration based on polarity of access, number of prior write cycles, and decoder distance. This dynamic adjustment ensures memory cells are programmed effectively while simultaneously protecting select device retention characteristics by reducing exposure to harmful programming conditions.
Solution Approach 2:
The patent implements feedback by using information about the state of select devices (polarity of access, prior write cycles, decoder distance) to determine appropriate programming pulse parameters. This feedback mechanism allows the system to optimize memory cell programming while accounting for the impact on select device retention, adjusting parameters in real-time based on the current state of the memory structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces errors and increases the lifespan of memory devices by optimizing the programming pulses for select devices, expanding the read window and improving overall memory stack performance.
Implementation Method 1
phase change memory control including a word line (WL) control module and a bit line (BL) control module
Implementation Method 2
Other non-volatile memories such as phase change (PRAM) use other physical phenomena such as a physical material change
Data Source
Figure 1A~1B
Figure 2A~2B
Figure 3
AI summary
Technology for a memory device is described. The memory device can include an array of memory cells and a memory controller. The memory controller can receive a request to program a memory cell within the array of memory cells. The memory controller can select a current magnitude and a duration of the current magnitude for a programming set pulse based on a polarity of access for the memory cell, a number of prior write cycles for the memory cell, and electrical distances between the memory cell and wordline/bitline decoders within the array of memory cells. The memory controller can initiate, in response to the request, the programming set pulse to program the memory cell within the array of memory cells. The selected current magnitude and the selected duration of the current magnitude can be applied during the programming set pulse.