Signal Generating Circuit for Stable Memory Pulse Widths
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor memories experience variations in clock signal periods due to process differences, leading to errors in signal pulse widths that exceed standard requirements, particularly under different process corners like Slow-Slow and Fast-Fast processes.
Innovation Solution
A signal generating circuit comprising a clock circuit, a controlling circuit, and a generating circuit that adjusts the target signal's pulse width by determining the target time length based on the internal clock signal and control signal, ensuring the pulse width remains within specified limits regardless of process variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a ring oscillator generates clock signals in semiconductor memory, then the memory can operate at high speeds, but the clock signal period varies due to process differences, causing signal pulse width errors to exceed specifications
Solution Approach 1:
The patent changes the parameter of clock signal generation from fixed ring oscillator frequency to dynamically adjustable frequency based on process corner detection. The system detects which process corner (SS, TT, FF) the memory operates on and adjusts the clock signal frequency accordingly, thereby maintaining accurate pulse widths despite manufacturing variations.
Solution Approach 2:
The patent implements a feedback mechanism where the system detects the actual process corner through calibration and uses this information to adjust the clock signal frequency. The detection result feeds back to the clock generation circuit, creating a closed-loop system that compensates for process variations and maintains signal accuracy.
2Manufacturing precision
If the clock signal frequency is adjusted to compensate for process variations, then signal accuracy improves, but the system complexity increases due to additional control circuits
Solution Approach 1:
The patent introduces dynamic adjustment capability to the clock generation system, allowing it to adapt its frequency based on detected process conditions. This dynamic behavior enables the system to maintain accuracy across different process corners without requiring completely separate circuits for each corner.
Solution Approach 2:
The patent designs a universal calibration and control mechanism that handles multiple process corners (SS, TT, FF) through a single integrated system. The same basic circuit structure performs calibration, detection, and adjustment functions across all process variations, reducing overall system complexity compared to having dedicated circuits for each corner.
Data Source
AI summary
A signal generating circuit includes the following: a clock circuit, configured to receive an external clock signal to generate an internal clock signal; a controlling circuit, configured to generate a control signal according to the frequency of the external clock signal; and a generating circuit, connected with the clock circuit and the controlling circuit respectively, and configured to receive the internal clock signal, the control signal and a flag signal to generate a target signal. When the flag signal changes from a first level to a second level, the target signal is changed from a third level to a fourth level, and after the target signal maintains the fourth level for a target time length, the target signal is changed from the fourth level to the third level. The generating circuit is further configured to determine the target time length according to the internal clock signal and the control signal.