Memory Device Pump Clock Selection for Power Optimization

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Solution Overview

Problem

Current memory devices face inefficiencies in power consumption due to the lack of optimal voltage generation and clock frequency adjustment based on the number of data bits stored, leading to suboptimal performance and increased energy usage.

Innovation Solution

A memory device with a peripheral circuit that generates operating voltages based on a target pump clock and control logic that selects the appropriate pump clock based on the number of data bits to be stored, optimizing voltage levels for efficient memory operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If a fixed pump clock frequency is used for voltage generation, then the device complexity is reduced, but the power consumption increases due to inability to optimize based on data bit requirements

Engineering Contradiction:
Improvepower consumptionVSAvoiddevice complexity
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The pump clock frequency is made dynamic rather than fixed. The control logic adjusts the pump clock frequency based on the number of data bits to be stored, selecting from multiple available frequencies. This allows the system to optimize power consumption by using lower frequencies for smaller data operations while maintaining the ability to use higher frequencies when needed, without requiring a completely complex adaptive architecture.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the parameter of pump clock frequency based on operational requirements. Different pump clock frequencies are selected according to the number of data bits that need to be stored in the memory cells. This parameter adjustment enables power optimization by matching the clock frequency to the actual computational workload, avoiding unnecessary energy consumption from consistently high-frequency operation.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If voltage levels are optimized for specific memory operations, then the productivity is improved, but the device complexity increases due to additional control logic

Engineering Contradiction:
Improveoperational efficiencyVSAvoiddevice complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The control logic is segmented to handle different operations independently. The system divides the control function into identifying the operation type (read, program, erase) and selecting appropriate pump clock frequencies and voltage levels for each. This segmentation allows for optimized voltage generation for each operation type without requiring a monolithic complex control system, as each segment can be independently implemented and optimized.

Inventive Principle:
Principle #1Segmentation

3Use of energy by moving object

If the pump clock frequency is adjusted based on data bit requirements, then the use of energy is reduced, but the measurement precision required increases to determine appropriate clock selection

Engineering Contradiction:
Improvepower consumptionVSAvoidmeasurement precision
Core Design Contradiction:
Use of energy by moving objectVSMeasurement precision

Solution Approach 1:

The system changes the parameter of pump clock frequency based on operational requirements. Different pump clock frequencies are selected according to the number of data bits that need to be stored in the memory cells. This parameter adjustment enables power optimization by matching the clock frequency to the actual computational workload, avoiding unnecessary energy consumption from consistently high-frequency operation.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12020757B2Memory device for generating pump clock and operating method of the memory device
Publication Date: 2024.06.25 SK HYNIX INC
  • US12020757B2 patent drawing
  • US12020757B2 patent drawing
  • US12020757B2 patent drawing

AI summary

A memory device including a plurality of memory cells, a peripheral circuit, and control logic. The peripheral circuit is configured to generate a plurality of operating voltages used in a memory operation, based on a target pump clock, and perform the memory operation by using the plurality of operating voltages. The control logic is configured to select the target pump clock among a plurality of pump clocks, based on a number of data bits which selected memory cells on which the memory operation is to be performed among the plurality of memory cells store, and control the peripheral circuit to perform the memory operation on the selected memory cells.