Memory Sub-System QoS Weighting for I/O Latency
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Solution Overview
Problem
Conventional memory sub-systems face challenges in providing consistent Quality of Service (QoS) levels to multiple functions, particularly in NAND-based devices, where write operations are slow and asynchronous, interfering with incoming system I/Os, and background operations like garbage collection can unpredictably impact I/O performance.
Innovation Solution
The memory sub-system assigns function weights and operation weights to prioritize I/O operations, implementing a program/erase suspend/resume policy to manage QoS levels, ensuring predictable processing times and deterministic latency by adjusting latency based on function weights and suspending lengthy operations to execute fast I/O operations without delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If write operations are performed in NAND-based memory devices, then data can be stored, but the operations are slow and asynchronous, interfering with incoming system I/Os and reducing I/O performance
Solution Approach 1:
The patent segments I/O operations into different queues (read queue, write queue, background operation queue) and assigns different weights to each queue. This allows the system to prioritize read operations and background operations while managing write operations separately, thereby improving overall I/O performance despite the slow asynchronous nature of write operations in NAND-based memory devices
Solution Approach 2:
The patent implements dynamic weight adjustment for different operation queues based on system state and priorities. The weight values are not fixed but can be adjusted to change the scheduling behavior, allowing the system to adapt to varying workloads and prioritize operations dynamically to maximize I/O performance
2Reliability
If background operations like garbage collection are executed, then memory maintenance is performed, but they unpredictably impact I/O performance
Solution Approach 1:
The patent separates background operations into a dedicated queue with its own weight, distinct from the I/O operation queues. This segmentation allows background operations to be scheduled independently and predictedably, preventing them from unpredictably impacting I/O performance while still ensuring memory maintenance is performed
Solution Approach 2:
The patent uses weight-based scheduling that can respond to system conditions. By adjusting weights based on system state, the system can dynamically balance between performing background maintenance operations and maintaining high I/O performance, creating a feedback mechanism that adapts to workload changes
3Reliability
If function weights are assigned to prioritize operations, then predictable QoS levels are achieved, but device complexity increases
Solution Approach 1:
The patent uses weight values as adjustable parameters to control operation prioritization. By changing weight parameters rather than implementing complex scheduling logic, the system achieves predictable QoS levels through a simple parameter-based approach, keeping the complexity manageable while improving reliability
Data Source
AI summary
A processing device, operatively coupled with the memory device, is configured to provide a plurality of functions for accessing the memory device, wherein a function of the plurality of function receives input/output (I/O) operations from a host computing system. The processing device further determines a quality of service level of each function of the plurality of functions, and assigns to each function of the plurality of functions a corresponding function weight based on a corresponding quality of service level. The processing device also selects, for execution, a subset of the I/O operations, the subset comprising a number of I/O operations received at each function of the plurality of functions, wherein the number of I/O operations is determined according to the corresponding function weight of each function. The processing logic then executes the subset of I/O operations at the memory device.