Memory Array Quadrant Layout for Concurrent ACU and Refresh
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Solution Overview
Problem
Existing memory devices face inefficiencies in performing access count update (ACU) operations and refresh operations concurrently with access operations, leading to shortened tRAS timing and increased tRP timing, which affects performance.
Innovation Solution
The memory array is divided into quadrants, with separate row and column decoders for ACU and refresh operations, allowing these operations to be performed concurrently during tRAS timing without extending overall tRC.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Extent of automation
If access count update operations are performed during access operations, then access count tracking is achieved, but tRAS timing is shortened
Solution Approach 1:
The memory array is divided into quadrants with separate row and column decoders for different operations. Access count update operations are performed in one quadrant while access operations occur in another quadrant, allowing parallel execution without interfering with tRAS timing of the primary access operation.
Solution Approach 2:
The patent introduces a spatial dimension by using separate quadrants and decoders for different operations. This allows access count updates and refresh operations to occur in a different spatial domain (separate quadrants) from the primary access operations, enabling concurrent execution without timing conflicts.
2Reliability
If refresh operations are performed during access operations, then memory cell information is restored, but tRP timing is increased
Solution Approach 1:
The memory array is segmented into quadrants with dedicated row and column decoders. Refresh operations are performed in specific quadrants using separate decoder paths, allowing them to execute concurrently with access operations in other quadrants without extending the overall tRP timing.
Solution Approach 2:
The patent enables continuous operation by performing refresh operations in the background during access operations. The separate decoder architecture allows refresh actions to continue without interrupting the normal access operation timeline, maintaining continuous useful action in both operational modes.
3Productivity
If separate decoders are used for ACU and refresh operations, then concurrent operations are enabled, but device complexity increases
Solution Approach 1:
The memory device is divided into quadrants with separate row and column decoders for different operational modes. This segmentation enables concurrent access count update and refresh operations to proceed simultaneously in different quadrants, improving productivity despite the increased structural complexity.
Solution Approach 2:
The separate decoder structure serves multiple functions: it enables concurrent access operations and refresh operations, supports access count tracking, and maintains timing integrity. This multi-functionality justifies the increased device complexity by providing comprehensive operational capabilities.
Data Source
AI summary
A memory has a bank with at least two row decoders each of which control at least two portions of the bank. Each word line has an associated access count which is stored along a word line coupled to a different row decoder. For example, if the memory receives an activate command and a row address that specifies a first word line associated with the first row decoder, then a second word line in a second portion associated with the second row decoder is also activated and an access count along the second word line is read out and updated. When an access is performed, the memory determines if a background refresh may be performed in a third portion also associated with the second row decoder.