Memory Read/Write Queue Balancing Through Fullness Feedback
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Solution Overview
Problem
Existing DDR controllers fail to balance the ratio of read and write operations, leading to degraded performance in data reading and writing due to unbalanced execution of read and write instructions.
Innovation Solution
A memory control method that dynamically adjusts the read/write control strategy based on the fullness state of read and write queues by obtaining data parameters, updating the strategy when differences meet a preset condition, and controlling subsequent operations accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the controller switches read/write operations based on time length or instruction quantity, then the control method is simple, but the ratio between executed instructions and expected instructions becomes unbalanced
Solution Approach 1:
The patent introduces a feedback mechanism where the controller continuously monitors the fullness states of read and write queues, compares them with expected states, and dynamically adjusts read/write operation switching based on the detected imbalances. This closed-loop control ensures that the ratio of executed instructions matches the expected ratio, resolving the contradiction between simple control and precise balance.
Solution Approach 2:
The patent transforms the static read/write switching mechanism into a dynamic one by making the switching decision dependent on real-time queue fullness states. Instead of fixed time or instruction-based switching, the controller adaptively adjusts switching behavior based on current system conditions, achieving both operational simplicity and instruction ratio precision.
2Productivity
If the controller remains in one direction longer to execute more operations, then the operation throughput increases, but the performance of reading/writing data becomes degraded
Solution Approach 1:
The controller uses feedback from queue fullness monitoring to detect when imbalance is occurring and switches directions accordingly. This prevents prolonged operation in one direction that would degrade performance while still maintaining high throughput by efficiently processing accumulated operations before switching.
Solution Approach 2:
The patent implements periodic detection of queue fullness states and periodic switching between read and write operations. This regular monitoring and switching pattern ensures that neither read nor write operations are prolonged excessively, maintaining both high throughput and reliable performance.
Data Source
AI summary
A memory control method includes obtaining data parameters in a read queue and a write queue, updating a read/write control strategy according to the first detection result and the second detection result to obtain an updated read/write control strategy, and controlling subsequent read/write operations of a memory according to the updated read/write control strategy. The data parameters correspond to a first detection result of a quantity of data in the read queue and a second detection result of a quantity of data in the write queue. The first detection result is related to a degree of a fullness state of the read queue, and the second detection result is related to a degree of a fullness state of the write queue.