Memory Sub-System Quick Boot Core for Faster Initialization
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Solution Overview
Problem
Conventional boot processes in memory sub-systems are multi-phase and sequential, leading to latency and delayed availability of system functionality due to the need for sequential execution of ROM, bootloader, and firmware phases.
Innovation Solution
Employing a quick boot CPU core to perform a portion of the boot process independently of the multi-phase sequence, allowing concurrent execution of prioritized boot tasks alongside the primary CPU core.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a multi-phase sequential boot process is used, then system reliability is ensured through proper initialization, but boot response time increases due to sequential execution requirements
Solution Approach 1:
The patent divides the boot process into two independent segments: a first boot process handling basic system initialization and a second boot process handling advanced initialization tasks. These segments are executed in parallel on different CPU cores, allowing the system to maintain reliability through proper initialization while reducing boot response time by eliminating sequential execution constraints.
Solution Approach 2:
The first boot process performs preliminary initialization actions (basic system setup) before the second boot process begins its advanced initialization tasks. This preliminary action enables critical system functions to be available earlier, reducing overall boot response time while maintaining proper initialization sequences through coordinated execution.
2Device complexity
If a single CPU core performs all boot tasks, then device complexity is minimized, but productivity decreases due to sequential task execution
Solution Approach 1:
The patent segments boot tasks into two distinct sets: basic initialization tasks executed by a first CPU core and advanced initialization tasks executed by a second CPU core. This segmentation increases productivity by enabling parallel execution while keeping device complexity manageable through a straightforward multi-core architecture that follows conventional processing approaches.
Solution Approach 2:
The system dynamically allocates different boot task sets to different CPU cores based on task priority and dependency requirements. This dynamic approach optimizes boot task execution speed by allowing concurrent processing of independent tasks while maintaining the ability to handle complex initialization sequences through coordinated inter-core communication.
Data Source
AI summary
A system comprises a memory device and a primary processing device, operatively coupled with the memory device. The primary processing device loads a primary image and a quick boot image from the memory device. Responsive to loading the primary image and the quick boot image from the memory device, the primary processing device performs a first portion of a boot up operation using the primary image. A quick boot processing device operatively coupled with the memory device, loads the quick boot image from the primary processing device. Responsive to loading the quick boot image, the quick boot processing device performs a second portion of the boot up operation using the quick boot image.


