Shared Memory Power Rail Throttling for Peak Current Control

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Solution Overview

Problem

Conventional processor-based systems face challenges in managing peak current demand on shared power rails, particularly in devices with size constraints like extended reality devices and AI pins, where power management integrated circuits (PMICs) are limited in the number of power rails and buck converter size, leading to potential performance degradation.

Innovation Solution

A processor-based system that monitors current demand on a shared power rail and throttles operating parameters of processing units when demand exceeds a peak threshold, using a two-stage approach involving filter and mitigation look-up tables to reduce current demand dynamically.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple processing units access the memory system simultaneously through a shared power rail, then system productivity is improved, but peak current demand exceeds the PMIC's power delivery capability

Engineering Contradiction:
Improvesystem performanceVSAvoidpeak current demand
Core Design Contradiction:
ProductivityVSPower

Solution Approach 1:

The system dynamically adjusts processing unit operating parameters based on real-time current demand monitoring. When peak current thresholds are approached, the system throttles clock frequencies and voltages of selected processing units to reduce instantaneous power demand while maintaining overall system productivity through coordinated operation.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The invention changes operating parameters (clock frequency, voltage) of processing units dynamically. By modifying these parameters based on current demand conditions, the system can deliver high performance when power is available and reduce consumption when the shared power rail approaches its current limits.

Inventive Principle:
Principle #35Parameter changes

2Volume of moving object

If the PMIC is designed with limited power rails and buck converter size to meet size constraints, then device compactness is improved, but the power delivery capability is reduced

Engineering Contradiction:
Improvedevice sizeVSAvoidpower delivery capability
Core Design Contradiction:
Volume of moving objectVSPower

Solution Approach 1:

Instead of designing the PMIC to always deliver maximum possible power, the system uses a smaller PMIC with limited power delivery capability and compensates by implementing intelligent power management. The system selectively activates and throttles processing units based on real-time power availability, effectively extracting maximum useful work from the constrained power infrastructure.

Inventive Principle:
Principle #16Partial or excessive action

3Use of energy by stationary object

If the system throttles operating parameters of processing units to reduce current demand, then power consumption is reduced, but processing speed decreases

Engineering Contradiction:
Improvepower consumptionVSAvoidprocessing speed
Core Design Contradiction:
Use of energy by stationary objectVSSpeed

Solution Approach 1:

The system implements periodic monitoring of current demand and dynamically adjusts processing unit speeds accordingly. Rather than maintaining constant high performance, the system cycles through different performance levels based on power availability, allowing processing units to operate at high speeds when power is abundant and reducing speed when power is constrained.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS20260072467A1Processor-based system configured to dynamically mitigate peak current demand of a shared power rail powering a memory system
Publication Date: 2026.03.12 QUALCOMM INC
  • US20260072467A1 patent drawing
  • US20260072467A1 patent drawing
  • US20260072467A1 patent drawing

AI summary

Aspects disclosed in the detailed description include a processor-based system configured to dynamically mitigate peak current demand of a shared power rail powering a memory system. The processor-based system includes a plurality of processing units which utilize the memory system. The memory system is powered by the shared power rail. The processor-based system monitors a current demand of the shared power rail from the plurality of processing units, determines whether the current demand for the shared power rail exceeds a peak threshold, and, in response to the current demand exceeding the peak threshold, throttle one or more operating parameters of at least one of the plurality of processing units to reduce or slow access to the memory system and, thus, the current demand over the shared power rail.