Memory Power Rail Switching for Logic Voltage Droop Mitigation

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Solution Overview

Problem

In processor-based systems with multiple voltage domains, the intrinsic decoupling capacitance of memory arrays coupled to the logic power rail leads to voltage droops, necessitating additional intentional decoupling capacitance, which increases area and leakage power, while scaling down the logic power rail to conserve power affects performance.

Innovation Solution

A power rail selection circuit dynamically switches the memory arrays between the logic and memory power rails based on the operating voltage, coupling to the logic rail when above the minimum operating voltage and to the memory power rail when below it, thereby reducing the need for additional decoupling capacitance, and switching to the memory power when the logic voltage is below the threshold.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If memory arrays are coupled to the logic power rail to utilize intrinsic decoupling capacitance, then voltage droops are reduced, but additional intentional decoupling capacitance is required which increases area and leakage power

Engineering Contradiction:
Improvevoltage stabilityVSAvoiddecoupling capacitance area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent implements dynamic switching between logic power rail and memory power rail for memory arrays based on real-time voltage conditions. A voltage monitoring circuit detects when logic power rail voltage drops below a threshold and automatically switches the memory arrays to the memory power rail, which has dedicated decoupling capacitance. This dynamic adaptation eliminates the need for additional static decoupling capacitance in the logic domain while maintaining voltage stability during transient current events.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent introduces a power rail switching circuit as an intermediary between the logic power rail and memory power rail. This switching mechanism allows memory arrays to be selectively coupled to either power rail based on operational needs. The switching circuit includes control logic that monitors voltage conditions and transitions memory arrays between power rails, effectively mediating the power supply relationship to optimize both voltage stability and area utilization.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If additional intentional decoupling capacitance is added to logic blocks to mitigate voltage droops, then voltage stability is improved, but leakage power increases

Engineering Contradiction:
Improvevoltage stabilityVSAvoidleakage power
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The system dynamically switches memory arrays between logic power rail and memory power rail based on real-time voltage monitoring. When voltage droops are detected on the logic power rail, memory arrays are automatically transferred to the memory power rail which has dedicated decoupling capacitance. This dynamic switching eliminates the need for additional static decoupling capacitance in the logic domain, thereby reducing leakage power while maintaining voltage stability during transient events.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The memory domains serve the logic domains by providing their intrinsic decoupling capacitance through the switching mechanism. When switched to the logic power rail, memory arrays' inherent capacitance helps stabilize the logic power rail during transient current events. This self-service approach allows the memory domain to contribute to logic domain stability without requiring additional dedicated decoupling capacitance in the logic domain, thus reducing leakage power.

Inventive Principle:
Principle #25Self-service

3Use of energy by moving object

If logic power rail voltage is scaled down to conserve power, then power consumption is reduced, but performance decreases

Engineering Contradiction:
Improvepower consumptionVSAvoidperformance
Core Design Contradiction:
Use of energy by moving objectVSProductivity

Solution Approach 1:

The patent segments the power supply into distinct logic power rail and memory power rail domains with independent voltage control. This segmentation allows the logic power rail to be scaled down to lower voltages for power conservation while the memory power rail maintains higher voltage levels required for memory operation functionality. Critical paths involving memory arrays can operate at higher voltages through this segmented architecture, preserving performance while reducing overall power consumption.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies different voltage levels to different parts of the system based on local requirements. The logic domain can operate at scaled-down voltages for power efficiency, while the memory domain maintains higher voltage levels necessary for its operational characteristics. This local quality differentiation allows each domain to operate optimally at its own voltage level, achieving both power conservation and performance preservation in critical paths.

Inventive Principle:
Principle #3Local quality

Data Source

PatentEP3283936B1Selective coupling of power rails to a memory domain(s) in a processor-based system
Publication Date: 2026.01.07 QUALCOMM INC
  • EP3283936B1 patent drawingFigure 1
  • EP3283936B1 patent drawingFigure 2
  • EP3283936B1 patent drawingFigure 3

AI summary

Selective coupling of power rails to memory domain(s) in processor-based system, such as to reduce or avoid the need to provide intentional decoupling capacitance in logic domain(s) is disclosed. To avoid or reduce providing additional intentional decoupling capacitance in logic domain to mitigate voltage droops on logic power rail, power rail selection circuit is provided. The power rail selection circuit is configured to couple memory domain to a logic power rail when the logic power rail can satisfy a minimum operating voltage of memory arrays. The additional intrinsic decoupling capacitance of the memory arrays is coupled to the logic power rail. However, if the operating voltage of the logic power rail is scaled down below the minimum operating voltage of the memory arrays when the logic domain does not need higher operation functionality, the power rail selection circuit is configured to couple the memory domain to separate memory power rail.