Memory Testing With Random CAS Instruction Insertion
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Solution Overview
Problem
Existing memory testing methods fail to simulate all possible scenarios of memory usage due to limitations in inserting different Column Address Strobe (CAS) instructions, leading to low scenario coverage and complex operations.
Innovation Solution
A method and device for testing memory that involves randomly generating and inserting valid and redundant CAS instructions, as well as invalid commands, to ensure the proper execution of instruction signals, thereby enhancing the randomness and accuracy of the test.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If different CAS instructions are inserted as much as possible to improve test accuracy, then measurement precision is improved, but device complexity increases due to protocol specification constraints
Solution Approach 1:
The patent applies dynamics by making the CAS instruction insertion flexible and adaptive rather than fixed. The testing device dynamically determines whether to insert valid CAS instructions, redundant CAS instructions, or invalid commands based on random selection and protocol compliance checks, allowing the system to adapt between different instruction types to balance test coverage and operational simplicity
Solution Approach 2:
The patent changes the parameters of CAS instruction insertion by introducing randomness in instruction type selection (valid vs. redundant vs. invalid) and timing. This parameter variation allows comprehensive testing of memory under different conditions while maintaining protocol compliance, resolving the contradiction between test diversity and operational complexity
2Reliability
If protocol specification constraints are strictly followed to ensure operation validity, then reliability is improved, but scenario coverage decreases due to limited CAS instruction variation
Solution Approach 1:
The patent applies partial action by selectively inserting only some CAS instructions (valid, redundant, or invalid) rather than inserting all possible types. This partial insertion strategy maintains protocol compliance for valid instructions while using redundant and invalid instructions to expand scenario coverage, achieving both reliability and versatility
Solution Approach 2:
The patent uses redundant CAS instructions as intermediaries between valid protocol-compliant instructions and invalid commands. These redundant instructions serve as a bridge that expands testing scenarios while maintaining overall protocol validity, allowing the system to explore edge cases without completely violating protocol specifications
3Adaptability or versatility
If random CAS instruction insertion is implemented to simulate all usage scenarios, then adaptability is improved, but operation complexity increases
Solution Approach 1:
The patent applies self-service by implementing automated random selection and insertion logic within the testing device itself. The system autonomously determines instruction types, performs protocol compliance checks, and inserts appropriate CAS instructions without requiring manual configuration, thereby achieving high scenario adaptability while keeping operations simple through automation
Data Source
AI summary
A method and a device for memory testing, and a computer-readable storage medium are provided. In the method, an instruction signal is sent to the memory, the instruction signal comprising a randomly generated write instruction or read instruction; a valid Column Address Strobe (CAS) instruction for ensuring running of the instruction signal is randomly inserted before the instruction signal by detecting a specific type of the instruction signal, and at least one of a redundant CAS instruction or invalid command irrelevant to the instruction signal is randomly generated and inserted; and the memory is enabled to run the instruction signal, the inserted valid CAS instruction, and the at least one of the redundant CAS instruction or the invalid command, and the running of the memory is tested.