Memory Device Randomizing Current Consumption via Delay Controller
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Solution Overview
Problem
Secure storage devices face vulnerabilities to invasive and non-invasive attacks, such as radiation and side-channel attacks, which allow hackers to access or extract sensitive information by analyzing power consumption and electromagnetic radiation patterns.
Innovation Solution
Introducing randomness or pseudo-randomness in the timing of current consumption during read operations by using a delay controller to pseudo-randomly or randomly select delay periods for data bit output, thereby creating unpredictable current consumption signatures that make it difficult for hackers to extract sensitive information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If deterministic timing is used for data bit output, then operational precision is improved, but security against side-channel attacks deteriorates
Solution Approach 1:
The patent applies dynamics by making the timing of data bit output variable rather than fixed. A delay controller randomly or pseudo-randomly selects delay periods for different data bits, causing the current consumption signature to change dynamically with each read operation. This prevents hackers from correlating consistent timing patterns with specific data values, thereby securing the device against differential power analysis while maintaining operational precision through controlled variability.
2Object-affected harmful factors
If random delay periods are introduced for data bit output, then security against side-channel attacks is improved, but timing predictability deteriorates
Solution Approach 1:
The patent changes the timing parameter of data bit output from a fixed value to a variable range. The delay controller introduces random or pseudo-random delay periods that fall within a specified range, altering the temporal characteristics of current consumption. This parameter change ensures that even though the absolute timing is unpredictable, the operational completeness is maintained, achieving security against timing-based side-channel attacks while preserving functional correctness.
3Productivity
If all data bits are output simultaneously, then read operation speed is improved, but current consumption signature analysis becomes vulnerable
Solution Approach 1:
The patent segments the simultaneous output of all data bits into sequential or near-sequential output with random delays between them. Instead of outputting all bits at once, the delay controller introduces random delay periods for individual bits or groups of bits. This segmentation disperses the current consumption signature over time with unpredictable patterns, preventing hackers from analyzing the aggregate power consumption signature to extract sensitive information, while still completing the read operation efficiently.
Data Source
AI summary
In some implementations, a memory device includes a plurality of memory cells, each memory cell storing a plurality of data bits; an input/output interface that is configured to, in response to receiving a read signal and an address value that identifies a specific memory cell in the plurality of memory cells, output a plurality of data bits corresponding to the identified specific memory cell; and a delay controller that is configured to delay the outputting to the input/output interface of at least one of the plurality of data bits based on a randomly selected or pseudo-randomly selected delay value. The memory device can further include a delay block having a plurality delay paths having varying delays, and randomly selecting or pseudo-randomly selecting the delay value can include randomly selecting or pseudo-randomly selecting one of the plurality of delay paths through which to transmit a control signal.