Memory Rank Intermediate Buffer for Parallel Column Access
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Solution Overview
Problem
Conventional memory systems using DRAM suffer from performance degradation due to sequential data reading across ranks, leading to time delays and reduced channel utilization, as they cannot perform column access operations simultaneously across multiple ranks.
Innovation Solution
Incorporating an intermediate buffer within each rank that allows for selective data transmission and reception between rank buses and the memory controller, enabling rank-level parallelism by executing read/write operations on multiple ranks concurrently through rank-level and channel-level commands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If multiple ranks share a common rank bus for data transmission, then device complexity is reduced, but column access operations cannot be performed simultaneously across multiple ranks leading to sequential processing
Solution Approach 1:
The patent segments the data transmission path by introducing intermediate buffers within each rank that can independently interface with the rank bus. This allows different ranks to simultaneously perform column access operations by buffering data locally, eliminating the bottleneck of shared bus sequential access while maintaining the simplicity of the rank bus structure.
Solution Approach 2:
The intermediate buffer acts as an intermediary component between the rank bus and the memory arrays. It enables simultaneous column access operations across multiple ranks by temporarily storing data within each rank, allowing the rank bus to serve multiple ranks in parallel without direct conflicts.
2Productivity
If an intermediate buffer is added within each rank to enable simultaneous column access operations, then parallel processing capability is improved, but device complexity increases
Solution Approach 1:
The intermediate buffer is designed with dynamic control logic that responds to command signals from the memory controller. The buffer's enable signal is dynamically activated only when needed for simultaneous column access operations, allowing the buffer to remain inactive during row access operations, thus reducing overall system complexity while enabling parallel processing when required.
Solution Approach 2:
The intermediate buffer's operational state is changed based on the type of command received. During row access operations, the buffer is disabled or placed in a high-impedance state, while during column access operations, it is enabled to facilitate simultaneous data transmission. This parameter-based control allows the same hardware structure to serve multiple functions without increasing complexity.
3Loss of energy
If sequential data reading is performed across multiple ranks through a shared bus, then channel utilization is reduced, but data collision is prevented
Solution Approach 1:
The intermediate buffer performs preliminary data buffering within each rank before data needs to be transmitted through the shared bus. By preparing data in advance at the rank level, the system can initiate column access operations simultaneously across multiple ranks, improving channel utilization without causing data collisions on the shared bus.
Data Source
AI summary
A memory system may include: a memory controller; a plurality of ranks; and a rank shared bus configured to couple the memory controller and the plurality of ranks. Each of the plurality of ranks may include: a plurality of banks; a rank bus coupled to the plurality of banks and configured to selectively transmit data to the rank shared bus or an intermediate buffer and selectively receive data from the rank shared bus or the intermediate buffer; and an intermediate buffer configured to be selectively coupled to the rank bus or the rank shared bus, according to a first signal from the memory controller.