Memory Rank Clock-Edge Selection for Inter-Rank Command Timing
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Solution Overview
Problem
Memory systems with multiple memory ranks operating in independent time domains face challenges in command path utilization due to inter-rank clock skew, leading to increased latency and reduced throughput, especially in systems requiring high command signaling bandwidth.
Innovation Solution
Implement phase-calibrated rank-specific timing signals and dedicated CA links to compensate for inter-rank clock skew, allowing for fine-interleaving of commands without significant timing penalties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory ranks operate in independent time domains with shared command path, then memory capacity is increased, but timing penalties and latency increase due to time-domain switching delays
Solution Approach 1:
The patent segments the command path by providing dedicated command paths for each memory rank. This allows simultaneous command transmission to multiple ranks without time-domain switching delays, resolving the contradiction between increased memory capacity and reduced latency by eliminating the shared resource bottleneck.
Solution Approach 2:
The patent introduces phase calibration circuits as intermediaries that adjust the timing of clock signals for each memory rank. These circuits compensate for inter-rank clock skew and enable precise timing alignment, allowing memory ranks to operate in independent time domains while maintaining synchronized command sampling.
2Productivity
If memory systems use micro-threading or module-threading to increase command signaling bandwidth, then data throughput is improved, but command path utilization increases to the point where insufficient time remains for time-domain switching
Solution Approach 1:
By segmenting the command path into dedicated channels for each memory rank, the patent enables parallel command transmission that supports micro-threading and module-threading without competing for shared bandwidth. This resolves the contradiction by providing sufficient command signaling bandwidth to high-productivity applications while eliminating time-domain switching delays.
Solution Approach 2:
The patent enables continuous command transmission to multiple memory ranks simultaneously through dedicated command paths and phase calibration. This eliminates idle time during rank switching and maintains continuous useful action, resolving the contradiction between high command signaling bandwidth utilization and sufficient time for time-domain switching.
3Loss of time
If designers limit memory systems to a single rank to avoid rank-switch timing penalties, then latency is reduced, but memory capacity is sacrificed
Solution Approach 1:
The patent segments the command path into dedicated channels for each memory rank, allowing multiple ranks to operate simultaneously without timing penalties. This resolves the contradiction by enabling designers to utilize multiple memory ranks for increased capacity while maintaining low latency through parallel command transmission.
Data Source
AI summary
In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such “microthreading” provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends.