Memory Rank Design for Graph Applications with Reduced ECC Overhead
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Traditional memory architectures are inefficient for graph-related applications that require accessing smaller, scattered data units, as they are optimized for spatial and temporal locality, leading to high ECC overhead in programmable unified memory architectures (PUMA) when using commonly available memory chips.
Innovation Solution
Implementing a memory rank design using X4 DDR4 or DDR5 memory chips, where two chips store raw data and one chip stores ECC information, reducing ECC overhead to 50% and ensuring adequate ECC protection regardless of data patterns, with ECC striping approaches that minimize corrupted symbols.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional memory architecture is used, then spatial and temporal locality is optimized, but ECC overhead increases for graph applications
Solution Approach 1:
The memory channel is divided into multiple ranks, each containing multiple memory chips. Within each rank, chips are organized to separate data storage and ECC storage functions. This segmentation allows graph applications to access smaller data units efficiently while maintaining ECC protection through the distributed chip architecture.
Solution Approach 2:
Different memory chips within a rank are assigned different functions: some chips store raw data while others store ECC information. This local differentiation optimizes the memory architecture for graph applications by ensuring that data and its corresponding ECC are stored in specific locations, improving access patterns while maintaining reliability.
2Length of moving object
If X8 memory chips are used, then data bus width is increased, but ECC overhead becomes excessive
Solution Approach 1:
The memory channel is divided into multiple ranks, each containing multiple memory chips. Within each rank, chips are organized to separate data storage and ECC storage functions. This segmentation allows graph applications to access smaller data units efficiently while maintaining ECC protection through the distributed chip architecture.
Solution Approach 2:
Different memory chips within a rank are assigned different functions: some chips storeraw data while others store ECC information. This local differentiation optimizes the memory architecture for graph applications by ensuring that data and its corresponding ECC are stored in specific locations, improving access patterns while maintaining reliability.
3Productivity
If data is accessed in large chunks, then memory bandwidth is utilized, but access to scattered data units becomes inefficient
Solution Approach 1:
The memory channel is divided into multiple ranks, each containing multiple memory chips. Within each rank, chips are organized to separate data storage and ECC storage functions. This segmentation allows graph applications to access smaller data units efficiently while maintaining ECC protection through the distributed chip architecture.
Solution Approach 2:
The memory architecture allows dynamic adjustment of access patterns by enabling the system to switch between accessing data in large chunks for bandwidth-intensive operations and accessing smaller scattered units for graph applications, optimizing performance based on workload requirements.
Data Source
AI summary
An apparatus is described. The apparatus includes a rank of memory chips to couple to a memory channel. The memory channel is characterized as having eight transfers of eight bits of raw data per burst access. The rank of memory chips has first, second and third X4 memory chips. The X4 memory chips conform to a JEDEC dual data rate (DDR) memory interface specification. The first and second X4 memory chips are to couple to an eight bit raw data portion of the memory channel's data bus. The third X4 memory chip to couple to an error correction coding (ECC) information portion of the memory channel's data bus.