Memory Rank IPD/APD Management for Lower Power and Fast Access
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Solution Overview
Problem
Existing memory systems with multiple ranks face challenges in balancing power consumption and high-speed operation due to inefficiencies in rank interleaving and idle/non-power down states, which affect performance in mobile devices.
Innovation Solution
A memory controller is employed to manage power states by causing memory ranks to enter idle power down (IPD) or active power down (APD) states based on data toggle times and page access patterns, reducing unnecessary power consumption and data bubbles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the non-target rank is maintained in idle non-power down or active non-power down state, then memory access speed is maintained, but power consumption increases due to IDD2N or IDD3N parameter current
Solution Approach 1:
The patent implements dynamic power state management by transitioning memory ranks between active, idle non-power down, and power down states based on access patterns. The memory controller dynamically determines when to enter IPD or APD states by monitoring data toggle times and comparing them against minimum gain duration thresholds, allowing the system to adapt power consumption to actual workload requirements while maintaining performance when needed.
Solution Approach 2:
The patent changes the power state parameter of memory ranks based on operational conditions. By monitoring data toggle time and comparing it to IPD minimum gain duration, the system transitions between different power states (active, idle non-power down, power down) to optimize the balance between speed and power consumption, directly applying parameter changes to resolve the contradiction.
2Use of energy by moving object
If the non-target rank enters IPD or APD state, then power consumption is reduced, but memory access performance may be degraded due to additional state transition delays
Solution Approach 1:
The patent applies preliminary action by monitoring data toggle times and predicting when a memory rank will remain idle for extended periods. By comparing the data toggle time against the IPD minimum gain duration threshold before transitioning to power down state, the system ensures that the rank will remain inactive long enough to justify the state transition, thereby avoiding performance degradation from unnecessary transitions while still achieving power savings.
Solution Approach 2:
The patent implements feedback mechanisms by continuously monitoring data access patterns and data toggle times, then using this information to determine optimal power state transitions. The system feedback loop compares actual data toggle times against minimum gain duration thresholds to dynamically adjust power states, ensuring that transitions to IPD or APD states occur only when they will not degrade overall memory access performance.
3Use of energy by moving object
If rank interleaving operations are reduced, then power consumption is reduced, but memory access efficiency may be impacted
Solution Approach 1:
The patent applies segmentation by dividing the memory system into multiple independent ranks that can be managed separately. Each rank can be independently transitioned to IPD or APD states based on its own access patterns, allowing the system to reduce power consumption in inactive ranks without impacting the performance of active ranks, thus maintaining overall memory access efficiency while reducing total power consumption.
Data Source
AI summary
Provided are electronic devices and methods for power reduction in systems with multiple memory ranks. The electronic device includes a memory system including first and second memory ranks and a memory controller connected to the memory system and configured to control power of the memory system. The memory controller being configured to cause the first memory rank to enter an idle power down (IPD) state during memory access in which a data toggle time without a data bubble is equal to or greater than an IPD minimum gain duration in another bank access for the second memory rank.