Memory Rank ODT Control for Signal Integrity and Lower Power

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

On-die termination (ODT) in semiconductor integrated circuits enhances signal integrity but increases power consumption, necessitating a method to reduce power consumption while maintaining signal integrity.

Innovation Solution

Implementing a method where ODT circuits are enabled in an initial state during power-on, enabled during write operations for target memory ranks, and disabled during read operations, while maintaining enabled states for non-target memory ranks, allowing for static ODT control and reduced power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If ODT circuits are enabled to enhance signal integrity, then signal reflection is reduced, but power consumption increases

Engineering Contradiction:

Improvesignal integrityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent implements dynamic ODT control where the termination state of memory ranks changes based on operation type. During write operations, ODT is enabled for both target and non-target ranks. During read operations, ODT is enabled only for non-target ranks while the target rank ODT is disabled. This dynamic adjustment resolves the contradiction by adapting the power-consuming ODT feature only when necessary for signal integrity.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent applies different ODT configurations to different memory ranks based on their role in the current operation. Target memory ranks receive different ODT treatment compared to non-target ranks. This local differentiation allows the system to optimize signal integrity where needed while reducing power consumption where it is not required.

Inventive Principle:

Principle #3Local quality

2Reliability

If ODT circuits are enabled during read operations for target memory rank, then signal integrity is maintained, but unnecessary power consumption occurs

Engineering Contradiction:

Improvesignal integrityVSAvoidstandby power consumption

Core Design Contradiction:

ReliabilityVSLoss of energy

Solution Approach 1:

The patent extracts the ODT function from the target memory rank during read operations, removing it when it is not needed for signal integrity. Only non-target ranks maintain ODT enabled during reads, effectively taking out the unnecessary power-consuming component while preserving signal integrity where required.

Inventive Principle:

Principle #2Taking out (Extraction)

3Reliability

If ODT is always enabled for all memory ranks, then signal reflection is minimized, but overall power consumption increases

Engineering Contradiction:

Improvesignal integrityVSAvoidsystem power consumption

Core Design Contradiction:

ReliabilityVSUse of energy by stationary object

Solution Approach 1:

The patent implements periodic adjustment of ODT states based on the operation cycle. During write operations, ODT is enabled for all ranks. During read operations, ODT is selectively disabled for target ranks. This periodic reconfiguration based on operation type reduces overall system power consumption while maintaining signal integrity during critical operations.

Inventive Principle:

Principle #19Periodic action

Data Source

PatentUS10916279B2Method of controlling on-die termination and system performing the same

Publication Date: 2021.02.09 SAMSUNG ELECTRONICS CO LTD

AI summary

A method of controlling on-die termination (ODT) in a multi-rank system including a plurality of memory ranks is provided. The method includes: enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank system is powered on; enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation.