Volatile Memory Rank Remapping via Buffer Chip
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Solution Overview
Problem
Volatile memory modules, such as DRAM, fail over time, leading to costly downtime and unnecessary replacement of entire modules due to single rank failures, which renders the entire module inoperable and disrupts computing processes.
Innovation Solution
Incorporating a buffer chip with rank remap control and dynamic serial presence detect sections to remap faulty ranks and pages, allowing the module to maintain operation by dynamically updating capacity and mapping, thereby reducing maintenance costs and minimizing performance degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the entire DRAM module is replaced upon single rank failure, then system reliability is improved, but device complexity and loss of time increase due to unnecessary full module replacement
Solution Approach 1:
The patent segments the DRAM module into multiple independent ranks, allowing individual rank failure isolation. The buffer chip contains separate buffer circuits for each rank, enabling selective buffering of specific failed ranks rather than requiring complete module replacement. This segmentation allows the system to maintain operation with partial rank failures.
Solution Approach 2:
The patent dynamically changes the operational parameters of the memory module by adjusting the buffer enable signals based on detected rank failures. The buffer chip modifies its buffering behavior in real-time, changing from full-module buffering to selective rank buffering, thereby adapting to the actual failure state and maintaining system reliability without full replacement.
2Reliability
If the entire DRAM module is replaced upon single rank failure, then system reliability is improved, but device complexity increases due to unnecessary full module replacement
Solution Approach 1:
The patent segments the DRAM module into multiple independent ranks, allowing individual rank failure isolation. The buffer chip contains separate buffer circuits for each rank, enabling selective buffering of specific failed ranks rather than requiring complete module replacement. This segmentation allows the system to maintain operation with partial rank failures.
Solution Approach 2:
The patent applies partial buffering action by enabling buffer circuits only for the specific ranks that have failed, rather than buffering all ranks. This partial action reduces the complexity overhead compared to full-module replacement while still maintaining system reliability for the affected ranks.
3Device complexity
If gaps in address space are left unfilled after rank failure, then device complexity is reduced, but productivity decreases due to rendering the entire module inoperable
Solution Approach 1:
The patent introduces a buffer chip as an intermediary component between the memory controller and the DRAM ranks. This buffer chip contains buffer circuits that mediate access to failed ranks by storing and forwarding data, thereby filling the functional gaps created by rank failures and maintaining module operability without increasing address space complexity.
Solution Approach 2:
The buffer chip serves multiple functions: it buffers data for healthy ranks, recovers data from failed ranks, and maintains address space continuity. This multi-functionality allows the same buffer infrastructure to handle both normal operation and failure recovery, maintaining productivity without proportionally increasing device complexity.
4Reliability
If replacement parts are used for failed modules, then reliability is improved, but loss of substance increases due to cost of replacement parts
Solution Approach 1:
The patent recovers functionality from failed ranks by using buffer circuits to capture and redirect data access to alternative ranks. Instead of discarding the entire module when a rank fails, the system recovers operational capacity by rerouting access through the buffer chip, thereby avoiding the cost of replacement parts while maintaining reliability.
Solution Approach 2:
The patent converts the harmful effect of rank failure into a beneficial outcome by using the buffer chip to automatically detect failures and reroute access to healthy ranks. This transforms what would be a catastrophic failure requiring expensive replacement into a manageable condition that maintains system operation and avoids replacement costs.
Data Source
AI summary
Embodiments of the inventive concept include a plurality of memory ranks, a buffer chip including a rank remap control section configured to remap a rank from among the plurality of memory ranks of the volatile memory module responsive to a failure of the rank, and a dynamic serial presence detect section configured to dynamically update a stated total capacity of the volatile memory module based at least on the remapped rank. In some embodiments, a memory module includes a plurality of memory ranks, an extra rank in addition to the plurality of memory ranks, the extra rank being a spare rank configured to store a new page corresponding to a failed page from among the plurality of ranks, and a buffer chip including a page remap control section configured to remap the failed page from among the plurality of ranks to the new page in the extra rank.