Memory Rank Selection via Dual Command Address Buses
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Solution Overview
Problem
The inefficiency of existing memory systems that require additional chip select signals for each memory rank, which complicates DIMM board design and pin-out layout, especially when multiple ranks need to be accessed simultaneously.
Innovation Solution
A memory system configuration where each memory rank receives command/address signals on both CAu and CAv terminals, allowing selection between ranks without the need for chip select signals, by using a controller to encode and decode specific commands to assign and select ranks through a command/address bus.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If additional chip select signals are used for each memory rank, then memory rank selection capability is improved, but device complexity and pin-out layout complexity increase
Solution Approach 1:
The patent merges the chip select function with the command/address signal lines by implementing two independent command/address buses (CA0 and CA1) that can simultaneously target different memory ranks. Instead of using separate CS signals, each rank has its dedicated CA bus that carries both command and address signals, eliminating the need for additional CS pins and reducing overall device complexity while maintaining the ability to select and access multiple ranks simultaneously
Solution Approach 2:
The command/address signal lines are given multi-functional capability by making them rank-specific. Each CA bus (CA0, CA1) can independently select and communicate with a specific memory rank, making the signal lines universal for both selection and data transmission purposes, thereby eliminating the need for dedicated chip select signals
2Adaptability or versatility
If additional chip select signals are used for each memory rank, then memory rank selection capability is improved, but pin-out layout complexity increases
Solution Approach 1:
The patent combines the chip select function with the existing command/address signal lines by creating rank-specific CA buses. Each memory rank is assigned a dedicated CA bus that handles both selection and communication, thereby eliminating the need for additional chip select pins and simplifying the pin-out layout while maintaining full memory rank selection capability
3Productivity
If multiple memory ranks are accessed simultaneously, then data bandwidth is improved, but device complexity increases
Solution Approach 1:
The patent segments the command/address signal lines into multiple independent buses (CA0, CA1, etc.), with each bus dedicated to a specific memory rank. This segmentation allows simultaneous access to multiple ranks through different CA buses without interference, enabling parallel operations that increase data bandwidth while keeping each individual bus simple and manageable
Solution Approach 2:
The patent merges the selection and data transmission functions into unified rank-specific command/address buses. Each CA bus can independently select and communicate with its associated memory rank, allowing simultaneous operations across multiple ranks without requiring complex additional control signals, thereby increasing productivity while managing device complexity
Data Source
AI summary
A multiple memory rank selection method and system assigns, based at least in part on decoding an assignment signal in a second command/address signal, a first terminal of a memory device to receive a first command/address signal and a second terminal of the memory device to receive the second command/address signal or assigns the first terminal of the memory device to receive the second command/address signal and the second terminal of the memory device to receive the first command/address signal. The multiple memory selection method and system decodes a selection signal encoded in the first command/address signal and enables the memory device based at least in part on the assignment signal and the selection signal.