Memory Programming Ratio Control for Smooth SLC-to-MLC Transitions

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Solution Overview

Problem

Memory systems experience sudden performance drops when switching between SLC and multiple level cell programming modes due to abrupt changes in performance, degrading user experience.

Innovation Solution

Implement adaptive performance tuning by determining a ratio for writing data to SLC and multiple level cell word lines based on operating parameters such as command queue depth, command size, host delay, and free space, using a mode register or algorithm to generate a weighted average.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the memory system switches between SLC and multiple level cell programming modes, then storage capacity and cost efficiency are improved, but performance stability deteriorates due to sudden performance drops

Engineering Contradiction:
Improvestorage capacityVSAvoidperformance stability
Core Design Contradiction:
Quantity of substanceVSStability of the object's composition

Solution Approach 1:

The patent implements dynamic mode ratio adjustment by continuously monitoring operating parameters (queue depth, command size, host delay, free space) and adapting the proportion of SLC versus multi-level cell programming accordingly. This dynamic adaptation allows the system to maintain performance stability while utilizing both storage modes, resolving the contradiction between storage capacity and performance stability.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the parameter of mode distribution ratio based on operating conditions. By adjusting the ratio of data written to SLC versus multi-level cell blocks according to real-time system state, the patent achieves both high storage utilization and stable performance characteristics across different operating scenarios.

Inventive Principle:
Principle #35Parameter changes

2Speed

If the memory system uses SLC programming mode, then performance speed is improved, but storage density and cost efficiency worsen

Engineering Contradiction:
Improveprogramming speedVSAvoidstorage density
Core Design Contradiction:
SpeedVSQuantity of substance

Solution Approach 1:

The patent applies different programming modes to different portions of data based on local requirements. High-priority or time-sensitive data is written to SLC blocks for fast access, while less time-critical data is written to multi-level cell blocks for higher density. This localized quality assignment optimizes both speed and storage density according to specific data characteristics.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The system dynamically adjusts the proportion of data directed to SLC versus multi-level cell blocks based on real-time operating parameters. When queue depth is low or host delay is high, more data is directed to SLC for faster processing. When free space is abundant or performance pressure is low, more data is directed to multi-level cell blocks for higher density utilization.

Inventive Principle:
Principle #15Dynamics

3Adaptability or versatility

If the memory system switches programming modes frequently, then adaptability to different storage needs is improved, but performance smoothness deteriorates due to abrupt transitions

Engineering Contradiction:
Improvemode adaptabilityVSAvoidperformance smoothness
Core Design Contradiction:
Adaptability or versatilityVSStability of the object's composition

Solution Approach 1:

The patent implements a feedback mechanism that continuously monitors operating parameters (queue depth, command size, host delay, free space) and uses this information to adjust the mode ratio. This closed-loop control ensures smooth, gradual transitions between programming modes rather than abrupt switches, maintaining performance smoothness while adapting to changing storage needs.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system employs dynamic ratio adjustment where the proportion of SLC versus multi-level cell programming changes gradually in response to operating conditions. This dynamic approach with smooth transitions maintains both adaptability to different storage scenarios and performance smoothness, avoiding abrupt mode switches that would degrade user experience.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS20260029958A1Adaptive performance tuning for memory systems
Publication Date: 2026.01.29 MICRON TECHNOLOGY INC
  • US20260029958A1 patent drawing
  • US20260029958A1 patent drawing
  • US20260029958A1 patent drawing

AI summary

Methods, systems, and devices for adaptive performance tuning for memory systems are described. A memory system may apply a programming mode ratio. For example, the memory system may write data to single-level cell (SLC) word lines and multiple level cell word lines according to a ratio. The memory system may determine the ratio according to operating parameters, such as a command queue depth, size of commands in the command queue, host delays, an amount of free space, or the like. The memory system may determine the ratio based on whether the operating parameters satisfy thresholds. That is, the memory system may compare each operating parameter to one or more operating parameter thresholds.