Memory Array Conductive Layers for RDL Isolation and Planarization
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Solution Overview
Problem
Conventional methods for forming redistribution layers (RDLs) in semiconductor devices face challenges such as short circuiting due to hard mask pattern misalignments and thickness variations, particularly because of the close proximity between adjacent RDLs, which affects chip size, power consumption, and memory access speed.
Innovation Solution
The method involves forming RDLs using a damascene process with dielectric layers, barrier layers, and conductive interconnects, where sputtering with inert gases like argon and oxygen is used to deposit and planarize conductive materials like ruthenium, ensuring insulation between adjacent RDLs and reducing surface unevenness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If RDLs are formed thick to have low resistance, then power consumption is reduced, but the distance between upper layer of one RDL and lower layer of adjacent RDL decreases, causing short circuits
Solution Approach 1:
The patent introduces dielectric layers as intermediary materials between adjacent RDLs. These dielectric layers act as insulating barriers that prevent electrical short circuits while allowing the RDLs to maintain their thick, low-resistance structure. The dielectric material fills the space between conductive layers, providing both mechanical support and electrical isolation.
Solution Approach 2:
The patent employs composite material structures combining conductive materials (for RDLs) and dielectric materials (for insulation). This composite approach allows simultaneous optimization of electrical conductivity in the RDL paths and electrical isolation between adjacent RDLs, resolving the contradiction between low resistance and short circuit prevention.
2Ease of manufacture
If conventional dry etching with hard masks is used to form RDLs, then manufacturing process is simple, but hard mask pattern misalignments and thickness variations cause short circuits
Solution Approach 1:
The patent applies preliminary planarization treatments to the substrate surface before depositing the RDL materials. This preliminary action ensures a flat, uniform baseline that compensates for subsequent deposition variations and reduces the impact of hard mask misalignments, thereby improving manufacturing precision without significantly complicating the overall process.
Solution Approach 2:
The patent modifies deposition parameters and material composition to achieve more uniform thin film thickness. By controlling deposition conditions and selecting materials with better film-forming properties, the patent reduces thickness variations that would otherwise lead to short circuits, while maintaining the relative simplicity of the manufacturing process.
3Area of stationary object
If distance between memory cells is shortened to reduce chip size, then chip area is reduced, but adjacent RDLs are placed closer together, increasing short circuit risk
Solution Approach 1:
The patent transitions from planar isolation to three-dimensional isolation by stacking dielectric layers vertically between RDLs. This dimensional approach allows RDLs to be placed closer together in the horizontal plane (reducing chip size) while maintaining adequate electrical isolation through the vertical dielectric barrier, effectively resolving the contradiction between compact layout and reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents short circuits between RDLs, enhances chip reliability, reduces power consumption, and minimizes chip size while maintaining high memory access speeds by ensuring precise insulation and uniformity of the conductive layers.
Implementation Method 1
sputtering with inert gases like argon and oxygen is used to deposit and planarize conductive materials like ruthenium
Implementation Method 2
sputtering with inert gases like argon and oxygen is used to deposit and planarize conductive materials like ruthenium
Data Source
AI summary
Apparatuses and methods for manufacturing semiconductor memory devices are described. An example method includes: forming a conductive layer and sputtering the conductive layer with gas. The conductive layer includes a first portion having a top surface having a first height; and a second portion having a top surface having a second height lower than the first height. Sputtering the conductive layer with gas may be performed to remove the first portion of the conductive layer and increase the second height of the second portion of the conductive layer concurrently.