Memory Device Re-evaluation via Interconnection Switching
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Solution Overview
Problem
Memory devices face challenges in reliably reading memory cells due to errors caused by imprecise evaluation units, leading to incorrect data interpretation and potential bit errors.
Innovation Solution
The memory device employs an interconnection unit to switch between two evaluation element assignments for each memory cell, allowing for re-evaluation using a different evaluation element in a second state, and an evaluation unit to determine and store deviation information to correct errors, thereby improving read operation reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single evaluation element is used to read memory cells, then the device complexity is reduced, but the reliability of read operations deteriorates due to errors from imprecise evaluation
Solution Approach 1:
The patent combines multiple evaluation elements (first evaluation element and second evaluation element) into a single memory device architecture. These evaluation elements work together to provide both initial reading and re-reading capabilities, merging their functions to achieve higher reliability without requiring separate independent systems.
Solution Approach 2:
The patent implements preliminary action by storing deviation information obtained during initial read operations. This deviation information is captured and stored before actual data retrieval operations, allowing the system to pre-compensate for evaluation element inaccuracies and improve subsequent read reliability.
2Reliability
If multiple evaluation elements are used with re-evaluation, then the reliability of read operations is improved, but the device complexity increases due to additional interconnection switching
Solution Approach 1:
The interconnection unit is designed with dynamic reconfigurability, allowing it to switch between different evaluation element assignments based on operational needs. This dynamic capability enables the system to adapt between using the first evaluation element for initial reads and the second evaluation element for re-reads, managing complexity through flexible rather than fixed architecture.
Solution Approach 2:
The interconnection unit serves multiple functions: it connects memory cells to the first evaluation element during initial read operations, connects them to the second evaluation element during re-read operations, and manages the storage of deviation information. This multi-functionality reduces the need for separate dedicated connection structures for each function.
3Reliability
If re-evaluation with alternative evaluation elements is performed, then errors are reduced through deviation information, but the reading time increases due to additional evaluation steps
Solution Approach 1:
The patent applies partial action by selectively performing re-reading operations only when deviation information indicates potential errors in the initial read. Instead of always performing full re-evaluation sequences, the system applies the additional evaluation step partially - only when and where needed based on the stored deviation information - thus reducing time loss while maintaining accuracy.
Data Source
AI summary
A memory device comprises a plurality of memory cells and a plurality of evaluation elements, wherein each evaluation element of the plurality of evaluation elements is connectable with a memory cell of the memory device. The memory device further comprises an interconnection unit configured for connecting the plurality of memory cells to a first assignment of evaluation elements in a first state and for connecting the same plurality of memory cells to a second assignment of the evaluation elements in a second state. The memory device comprises an evaluation unit configured for controlling the interconnection unit to transition from the first state to the second state. The evaluation unit is configured for evaluating the plurality of memory cells in the first state to obtain a first evaluation result, and for evaluating the plurality of memory cells in the second state to obtain a second evaluation result.