Memory Transaction Re-mapping for Peripheral Coherency
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Solution Overview
Problem
In computer systems, memory transactions involving peripherals can lead to coherency issues due to 'stale' values when peripherals access external memory directly, as cache values are not updated in external memory, requiring mechanisms to maintain coherency between cache and external memory.
Innovation Solution
The system employs a method to re-map memory transaction identifiers, replacing original identifiers with modified ones that the processor complex can handle, using a re-mapper circuit and interface circuit to ensure coherency and proper processing of requests and responses, particularly in systems-on-a-chip (SoC) environments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the processor complex uses a limited identifier bit size (e.g., 3-bit), then the device complexity is reduced and processing is simplified, but the adaptability to handle diverse memory transactions from multiple peripherals is limited
Solution Approach 1:
The patent introduces an intermediary translation mechanism that converts between different identifier bit sizes. The system uses a mapping table stored in configuration memory that correlates limited-bit identifiers (e.g., 3-bit) with extended-bit identifiers (e.g., 8-bit), allowing the processor complex to work with simple identifiers while maintaining compatibility with peripherals that require more identifier space.
Solution Approach 2:
The system dynamically changes the identifier parameter by selecting different mapping configurations based on the peripheral device type. The control unit adjusts the identifier translation parameters according to the specific peripheral being accessed, enabling the same processor complex to handle multiple peripheral types with different identifier requirements.
2Speed
If peripherals access external memory directly without cache involvement, then the speed of memory access is improved, but the coherency between cache and external memory deteriorates
Solution Approach 1:
The patent implements a feedback mechanism where the control unit monitors memory access patterns and determines when cache coherency updates are needed. When a peripheral accesses external memory, the control unit receives feedback about the access and decides whether to invalidate or update cache lines to maintain coherency, balancing speed and reliability.
Solution Approach 2:
The system performs preliminary actions by pre-establishing the identifier mapping tables and configuring the translation mechanism before memory transactions occur. This allows the system to maintain coherency protocols in advance, so when direct peripheral memory access happens, the coherency management is already in place to handle the transaction appropriately.
3Measurement precision
If the system maintains detailed identifier mapping tables, then the measurement precision of transaction tracking is improved, but the loss of time for processing and searching mappings increases
Solution Approach 1:
The mapping tables are pre-configured and stored in dedicated configuration memory during system initialization or device configuration phase. This preliminary action allows the runtime processing to simply perform direct table lookups rather than computing mappings in real-time, significantly reducing the time penalty while maintaining precise transaction tracking.
Solution Approach 2:
The identifier mapping system is segmented into separate lookup tables for different peripheral types and identifier formats. This segmentation allows the control unit to quickly select the appropriate table based on the peripheral type, avoiding the need to search through a single large comprehensive mapping structure, thus reducing processing time while maintaining accuracy.
Data Source
AI summary
Systems and methods for re-mapping memory transactions are described. In an embodiment, a method includes receiving a memory request from a hardware subsystem to a memory, replacing a first identifier with a modified identifier in the memory request, and transmitting the memory request to the memory through a processor complex. The method further includes receiving a response from the memory, determining that the response corresponds to the memory request, replacing the modified identifier with the first identifier in the response, and transmitting the response to the hardware subsystem. In some embodiments, a system may be implemented as a system-on-a-chip (SoC). Devices suitable for using these systems include, for example, desktop and laptop computers, tablets, network appliances, mobile phones, personal digital assistants, e-book readers, televisions, and game consoles.