Memory Read Decoding With Adaptive LLR Tables and ECC

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Solution Overview

Problem

Current memory systems face challenges in efficiently correcting errors in data read from memory devices due to variations in threshold voltage distributions of cell transistors, leading to inaccurate data retrieval and increased error correction times.

Innovation Solution

The implementation of a memory system with an error correction code (ECC) circuit that utilizes a combination of hard-bit and soft-bit decoding, along with Low-Density Parity Check (LDPC) coding, to detect and correct errors by converting LLR labels to LLR values using adaptive LLR tables, allowing for optimal read voltage adjustments and improved error correction capabilities.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If hard-bit decoding is used for error correction, then the decoding process is simple and fast, but the error correction capability is insufficient due to threshold voltage variations

Engineering Contradiction:
Improvedecoding speedVSAvoiderror correction capability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The decoding process is segmented into two distinct stages: hard-bit decoding for quick initial error correction, followed by soft-bit decoding for enhanced correction capability. This segmentation allows the system to benefit from both fast hard decisions and reliable soft information processing, resolving the contradiction between speed and capability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system dynamically selects decoding strategies based on error conditions. It performs hard-bit decoding first, and only transitions to soft-bit decoding when hard decoding fails or insufficient correction is achieved. This dynamic approach optimizes both speed and reliability by applying the appropriate method based on actual needs.

Inventive Principle:
Principle #15Dynamics

2Reliability

If soft-bit decoding with LLR conversion is used, then error correction capability is improved, but the decoding time increases significantly

Engineering Contradiction:
Improveerror correction capabilityVSAvoiddecoding time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system applies soft-bit decoding selectively rather than universally. It performs partial soft-bit processing only on bits that require correction after hard decoding, or uses truncated soft-bit information when full soft decoding is not necessary. This partial action maintains high error correction capability while reducing the time penalty of complete soft-bit processing.

Inventive Principle:
Principle #16Partial or excessive action

3Productivity

If fixed read voltage is used, then the read operation is simple and fast, but data retrieval accuracy deteriorates due to threshold voltage distribution variations

Engineering Contradiction:
Improveread operation speedVSAvoiddata retrieval accuracy
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The system performs preliminary threshold voltage distribution analysis and LLR table generation before actual data reading. By pre-characterizing the memory device and preparing adaptive lookup tables, the system can quickly adjust read operations without real-time complex calculations, maintaining both speed and accuracy.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system changes read voltage parameters dynamically based on detected threshold voltage shifts. It adjusts voltage levels and uses adaptive LLR tables that account for distribution variations, thereby maintaining high retrieval accuracy while keeping the read operation efficient through parameter adaptation rather than complex processing.

Inventive Principle:
Principle #35Parameter changes

4Measurement precision

If adaptive LLR tables are generated and used, then decoding accuracy is improved, but the system complexity increases

Engineering Contradiction:
Improvedecoding accuracyVSAvoidsystem complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The system uses lookup tables (LLR tables) that store pre-computed conversion data instead of performing complex real-time calculations. By copying and storing characteristic data in tabular form, the system achieves high decoding accuracy through simple table lookups, significantly reducing computational complexity while maintaining precision.

Inventive Principle:
Principle #26Copying

Data Source

PatentUS11537465B2Memory system
Publication Date: 2022.12.27 KIOXIA CORP
  • US11537465B2 patent drawing
  • US11537465B2 patent drawing
  • US11537465B2 patent drawing

AI summary

In general, according to an embodiment, a memory system includes a memory device including a memory cell; and a controller. The controller is configured to: receive first data from the memory cell in a first data reading; receive second data from the memory cell in a second data reading that is different from the first data reading; convert a first value that is based on the first data and the second data, to a second value in accordance with a first relationship; and convert the first value to a third value in accordance with a second relationship that is different from the first relationship.