Memory Device Write Defect Detection via Read-Back Verification
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Solution Overview
Problem
Existing memory systems face challenges in reliably writing data due to physical defects in word lines, leading to incorrect threshold voltage distributions and potential data loss, especially in NAND-type flash memory devices.
Innovation Solution
The memory system employs a defect detection mode during write operations, using a prefix command to store write data in a buffer and subsequently reading it back for comparison, allowing for the detection of physical defects and preventing data loss by updating status information based on comparison results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a write operation is performed in existing memory systems, then data can be stored in the memory cell array, but physical defects in word lines may cause incorrect threshold voltage distributions and data loss
Solution Approach 1:
The patent applies preliminary action by performing a read operation immediately after the write operation to verify the written data. The controller reads data from the memory cell array using the same word line and compares it with the originally written data. This preliminary verification action detects physical defects in word lines before data loss occurs, thereby improving data reliability without significantly increasing operational complexity.
Solution Approach 2:
The patent implements feedback by introducing a verification mechanism where the controller compares the read data with the written data and updates status information accordingly. This feedback loop enables the system to detect write failures caused by word line defects and notify the host device, ensuring data integrity while maintaining a relatively simple operational structure.
2Productivity
If traditional write operations are used without defect detection, then the write operation is simple and fast, but data loss occurs due to undetected physical defects in word lines
Solution Approach 1:
The patent performs a read operation as a preliminary verification step after writing data. This read operation uses the same word line and compares the retrieved data with the originally written data. By doing this preliminary check, the system maintains high write efficiency while simultaneously ensuring data integrity, as the verification occurs immediately without significant delay to the overall write process.
Solution Approach 2:
The controller implements feedback by comparing the read data with the written data and updating status information to reflect the verification result. This feedback mechanism ensures that data integrity is maintained by detecting and reporting write failures, thereby preventing data loss while preserving write operation efficiency.
3Reliability
If defect detection mode is implemented with read-back comparison, then data reliability is improved, but power consumption and latency increase
Solution Approach 1:
The patent performs the read operation as a preliminary verification step that is tightly integrated with the write operation. By conducting the read-back comparison immediately after writing and using the same word line, the system minimizes additional power consumption. The verification process leverages existing circuit resources and avoids repeated high-power operations, thereby maintaining energy efficiency while improving data reliability.
4Reliability
If defect detection mode is implemented with read-back comparison, then data reliability is improved, but write operation latency increases
Solution Approach 1:
The patent executes the read operation as a preliminary verification step that begins immediately after the write operation completes. By using the same word line and performing the read-back comparison in sequence without significant idle time, the system minimizes additional latency. The verification process is integrated into the write operation flow, ensuring that data reliability is improved with minimal time penalty.
Data Source
AI summary
A memory device according to one embodiment includes a memory cell array, bit lines, amplifier units, a controller, and a register. The memory cell array includes a memory cell that stores data nonvolatilely. The bit lines are connected to the memory cell array. The sense amplifier units are connected to the bit lines, respectively. The controller performs a write operation. The register stores status information of the write operation. The memory cell array includes a first storage region specified by a first address. The plurality of sense amplifier modules include a buffer region capable of storing data.