Memory Read Level Validation Using Bit Count Feedback
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Solution Overview
Problem
Existing memory device calibration techniques exhibit high latency and are ineffective in accurately adjusting read level voltages due to their reliance on 'blind' voltage distribution estimation, leading to potential misalignment with actual voltage distribution valleys.
Innovation Solution
Implementing memory device-originated bit count information to validate read level voltages by comparing actual and expected bit counts, allowing for precise adjustment of read levels to align with correct voltage distribution valleys.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If existing memory device calibration techniques are used to adjust read level voltages, then the process can be completed, but the latency is high and the accuracy is poor due to blind voltage distribution estimation
Solution Approach 1:
The patent implements a feedback mechanism where the memory device returns bit count information to the memory sub-system controller, which then validates and adjusts read level voltages based on the comparison between actual and expected bit counts. This closed-loop feedback system eliminates blind estimation and enables precise voltage adjustment while maintaining low latency through efficient feedback processing.
Solution Approach 2:
The memory device performs self-validation by generating and returning bit count information that reflects the actual voltage distribution. This self-service capability allows the memory device to provide its own calibration data, eliminating the need for external blind estimation techniques and reducing the overall calibration latency while improving accuracy.
2Ease of operation
If blind voltage distribution estimation is used for calibration, then the calibration process can proceed, but the read level voltages may be misaligned with actual voltage distribution valleys
Solution Approach 1:
The patent replaces the mechanical/blind estimation approach with an information-based validation system. Instead of relying on theoretical voltage distribution models, the system uses actual bit count information returned from the memory device to validate and adjust read level voltages, substituting empirical measurement for theoretical estimation and achieving precise alignment with actual voltage distribution valleys.
3Productivity
If read level voltages are not accurately validated, then the calibration process is faster, but data retrieval accuracy deteriorates
Solution Approach 1:
The patent implements a selective validation approach where bit count information is returned and validated for specific read level voltages that require adjustment. This partial action approach focuses calibration efforts only where needed, maintaining high calibration speed while ensuring data retrieval accuracy through targeted validation of critical read levels rather than comprehensive recalibration of all voltages.
Data Source
AI summary
Described are systems and methods for validating read level voltage in memory devices. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines; and a controller coupled to the memory array, the controller to perform operations comprising: causing a read level voltage to be applied to a specified wordline of the plurality of wordlines; determining a read level adjustment as a function of a sequential number of a margin valley corresponding to the read level voltage; and adjusting the read level voltage by applying, to the read level voltage, the read level adjustment.