Memory Cell Read Boost Timing for First and Second Read Margins

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Non-volatile memory devices face challenges in efficiently determining the read condition of memory cells, leading to increased read time and potential read disturb due to the difference in boost timing requirements between first and second read conditions.

Innovation Solution

A control circuit is configured to determine the read condition of a memory cell, allowing for dynamic adjustment of boost timing based on the read condition, thereby optimizing the read operation and reducing total read time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If a fixed boost timing is used for all read conditions, then the control circuit is simple, but read time increases and read disturb occurs

Engineering Contradiction:
Improveread timeVSAvoidcontrol circuit complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent applies dynamics by making the boost timing adjustable rather than fixed. The control circuit dynamically selects between a first boost timing for first read conditions and a second boost timing for second read conditions, allowing the system to adapt to different operational states and reduce read time when appropriate.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter of boost timing based on read conditions. By determining whether a first or second read condition exists and selecting the corresponding boost timing, the system optimizes read performance for different scenarios without requiring complete redesign of the control circuit.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If different boost timings are applied for different read conditions, then read time is reduced, but the control circuit becomes more complex

Engineering Contradiction:
Improveread operation efficiencyVSAvoidcontrol circuit complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The control circuit dynamically adapts its behavior based on detected read conditions. It selects appropriate boost timings (first or second) depending on whether first or second read conditions are present, thereby optimizing productivity without requiring complex hardware redesign.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes operational parameters (boost timing) based on detected conditions. By implementing parameter changes rather than structural complexity, the patent achieves improved productivity while keeping the control circuit relatively simple.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If boost timing is extended to cover all read conditions, then read disturb is minimized, but total read time increases

Engineering Contradiction:
Improveread operation reliabilityVSAvoidtotal read time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies local quality by providing different boost timings for different read conditions. Instead of using a single extended boost timing for all conditions, it uses a first boost timing for first read conditions and a second boost timing for second read conditions, optimizing both reliability and time efficiency locally for each scenario.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The system dynamically adjusts boost timing based on actual read conditions. This dynamic approach allows the control circuit to maintain reliability when needed while reducing unnecessary time delays, achieving an optimal balance between reliability and speed.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS20230386580A1Method to optimize first read versus second read margin by switching boost timing
Publication Date: 2023.11.30 SANDISK TECHNOLOGIES LLC
  • US20230386580A1 patent drawing
  • US20230386580A1 patent drawing
  • US20230386580A1 patent drawing

AI summary

An apparatus that comprises a plurality of memory cells and a control circuit coupled to the plurality of memory cells is disclosed. The control circuit is configured to perform a read operation. The read operation includes determining a read condition of a memory cell, where the read condition is of a plurality of read conditions and determining a boost timing for the memory cell, where the boost timing corresponds to the read condition.