Variable-Resistance Memory Read Circuit With Buffer-Equalized Sensing
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Solution Overview
Problem
Existing storage circuits face challenges in miniaturization and large-scaling due to increased wiring capacitance and slower read speeds, which are exacerbated by the differences in wiring distances for data and reference voltages, leading to potential memory cell data destruction and reduced read margins.
Innovation Solution
A storage circuit design with a memory cell array, resistance-voltage conversion circuits for each column, and analog buffer circuits or reference circuits with adjustable current driving capabilities to equalize signal transmission speeds, using variable resistance type elements and sense amplifiers for each column to enhance read speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If wiring is thickened to reduce resistance, then wiring resistance is reduced, but wiring capacitance increases
Solution Approach 1:
The patent changes the electrical parameters of the wiring by introducing buffer circuits that actively drive the bit lines, transforming the passive wiring characteristics into actively controlled signal transmission paths. This allows the system to overcome the inherent RC time constant limitations without physically changing the wiring dimensions.
Solution Approach 2:
Buffer circuits are introduced as intermediary components between the memory cells and the read circuitry. These buffer circuits act as mediators that amplify and reshape the signals, compensating for the RC delay effects of the wiring without requiring physical modification of the wiring itself.
2Loss of time
If on-resistance of read load transistors is made small to charge wiring capacitance rapidly, then wiring driving time is reduced, but read current becomes large causing memory cell data destruction
Solution Approach 1:
The patent segments the read operation into multiple stages by introducing buffer circuits that operate in sequence. The first buffer circuit charges the bit line capacitance, and subsequent buffer circuits amplify the signal, distributing the current demand across multiple devices rather than requiring a single high-current transistor.
Solution Approach 2:
The buffer circuits perform preliminary signal conditioning and amplification before the signal reaches the sense amplifier. This preliminary action ensures that the signal is fully developed and stable, eliminating the need for high read currents that would cause read disturb.
3Speed
If sense amplifier is disposed for each bit line to increase read speed, then read speed is improved, but wiring for transmitting reference voltage becomes long increasing wiring driving time
Solution Approach 1:
The patent merges the reference voltage distribution function into the existing bit line buffer circuit infrastructure. By using the same buffer circuit network to distribute both data signals and reference voltages, the patent eliminates the need for separate long reference voltage lines, thereby maintaining high read speed without the penalty of extended wiring.
4Area of moving object
If miniaturization of memory cell is pursued, then memory cell size is reduced, but on-resistance of read load transistors increases slowing down read operation
Solution Approach 1:
Buffer circuits are introduced as intermediary stages between the miniaturized memory cells and the read circuitry. These buffers compensate for the increased on-resistance of the read load transistors by providing active signal boosting, thereby maintaining high read speeds despite the smaller transistor dimensions required for miniaturization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design allows for miniaturization and large-scaling while increasing read speed by optimizing signal transmission through higher current driving capabilities, reducing wiring capacitance, and preventing memory cell destruction.
Implementation Method 1
a variable resistance type element, the variable resistance type element having a resistance value changing in at least two steps
Implementation Method 2
a resistance-voltage conversion circuit to convert a resistance value of a memory cell to be read in the memory cell array to a data voltage
Implementation Method 3
a sense amplifier to determine data stored in the memory cell to be read by receiving the data voltage and the reference voltage via first and second input terminals, respectively, and comparing both voltages with each other
Data Source
AI summary
A storage circuit includes a memory cell array of memory cells each including a variable resistance type element, a resistance-voltage conversion circuit RTj to convert a resistance value of a memory cell MCij to be read to a data voltage, a reference circuit and RTR to generate a reference voltage, a sense amplifier to determine read data by receiving the data voltage and the reference voltage via first and second input terminals, respectively, and comparing both voltages with each other, and an analog buffer circuit arranged between the resistance-voltage conversion circuit RTj and a first input terminal of the sense amplifier or between the reference circuit and RTR and a second input terminal of the sense amplifier. Current driving capability of the analog buffer circuit is large.