Semiconductor Memory Read Speed via Channel Reflection
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Solution Overview
Problem
Current semiconductor memory devices face challenges in achieving improved read speed due to the time-consuming process of reflecting and sensing data across cell strings, which affects the efficiency of data retrieval.
Innovation Solution
The proposed solution involves an operating method where data from a selected memory cell is reflected on a channel of a second cell string through a bit line, allowing for the sensing of electric charge variations to determine the data, and this process is optimized by sharing bit lines between cell strings and using a peripheral circuit with an address decoder and page buffer to manage voltages and connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is reflected and sensed across cell strings through bit lines, then data retrieval is achieved, but the process is time-consuming and reduces read speed
Solution Approach 1:
The patent applies preliminary action by pre-forming channels in the second cell string before data reflection occurs. The peripheral circuit forms channels in response to pass voltages applied to word line groups, so that when data needs to be read, the pathway is already prepared and ready for immediate charge transfer, eliminating the time required to create channels during the read operation itself.
Solution Approach 2:
The patent segments the memory structure into multiple word line groups (first and second word line groups) each associated with separate cell strings. This segmentation allows independent channel formation and data reflection processes to occur in parallel across different segments, reducing the overall time required for data retrieval by avoiding sequential processing of entire memory blocks.
2Device complexity
If bit lines are shared between cell strings, then device complexity is reduced, but measurement precision of electric charge may be affected
Solution Approach 1:
The patent introduces the second cell string as an intermediary structure that receives reflected data charges from the first cell string through the shared bit line. The peripheral circuit forms channels in the second cell string to capture these reflected charges, acting as a mediator that isolates the sensing process from the data storage cell string. This intermediary approach allows accurate charge measurement while utilizing shared bit lines, as the second cell string provides a dedicated sensing pathway.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances read operation speed by efficiently reflecting and determining data across cell strings, allowing for faster data retrieval and improved performance in semiconductor memory devices.
Implementation Method 1
reflecting data of a selected memory cell coupled to a selected word line of the first word line group, among memory cells of the first cell string, on the channel of the second cell string through the bit line
Data Source
AI summary
A semiconductor memory device according to an embodiment of the present invention includes a first cell string and a second cell string coupled to a first word line group and a second word line group, respectively. An operating method of the semiconductor memory device may include forming a channel in the second cell string by applying a pass voltage to the second word line group, reflecting data of a selected memory cell coupled to a selected word line of the first word line group, among memory cells of the first cell string, on the channel of the second cell string through the bit line, and determining the data of the selected memory cell by sensing a quantity of electric charge of the second cell string through the bit line.