3D Memory Read Circuit Using Current Comparison for Faster Access

Solution Overview

Problem

In memory devices with a large number of memory cells connected to a bit line, access time is increased, and power consumption is higher when using current sensing amplifiers compared to voltage sensing amplifiers, while circuit area is not optimized.

Innovation Solution

A memory device structure with a reading circuit and memory cells, where transistors in the reading circuit and memory cells include silicon and metal oxide in the channel formation region, allowing current-based data reading with reduced power consumption and circuit area by using a specific connection structure of transistors and capacitors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If a current sensing amplifier is used for data reading, then access time is shortened, but power consumption increases

Engineering Contradiction:

Improveaccess timeVSAvoidpower consumption

Core Design Contradiction:

Loss of timeVSUse of energy by moving object

Solution Approach 1:

The patent divides the sensing function into two separate circuits: a voltage sensing amplifier for reading data and a current sensing amplifier for sensing current. This segmentation allows each circuit to be optimized for its specific function, enabling fast access through voltage sensing while using current sensing only when necessary, thus reducing overall power consumption compared to always using a current sensing amplifier.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent dynamically switches between voltage sensing and current sensing modes based on the state of the bit line. The voltage sensing amplifier is used during normal read operations for fast access, while the current sensing amplifier is activated only when the bit line voltage is insufficient, providing adaptive performance optimization and power management.

Inventive Principle:

Principle #15Dynamics

2Quantity of substance

If more memory cells are electrically connected to one bit line to increase storage capacity, then storage capacity per unit area increases, but access time increases

Engineering Contradiction:

Improvestorage capacityVSAvoidaccess time

Core Design Contradiction:

Quantity of substanceVSLoss of time

Solution Approach 1:

The patent transitions from a planar memory architecture to a three-dimensional stacked architecture with multiple memory cell layers connected to bit lines. This dimensional change allows increasing the number of memory cells per bit line without proportionally increasing access time, as the stacked structure enables parallel access to multiple layers simultaneously, thus improving storage capacity while maintaining acceptable access times.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Use of energy by moving object

If a voltage sensing amplifier is used for data reading, then power consumption is reduced, but access time increases due to long precharge and discharge times

Engineering Contradiction:

Improvepower consumptionVSAvoidaccess time

Core Design Contradiction:

Use of energy by moving objectVSLoss of time

Solution Approach 1:

The patent divides the sensing function into two separate circuits: a voltage sensing amplifier for reading data and a current sensing amplifier for sensing current. This segmentation allows each circuit to be optimized for its specific function, enabling fast access through voltage sensing while using current sensing only when necessary, thus reducing overall power consumption compared to always using a current sensing amplifier.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent dynamically switches between voltage sensing and current sensing modes based on the state of the bit line. The voltage sensing amplifier is used during normal read operations for fast access, while the current sensing amplifier is activated only when the bit line voltage is insufficient, providing adaptive performance optimization and power management.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS20240221812A1Memory device, semiconductor device, and electronic device

Publication Date: 2024.07.04 SEMICON ENERGY LAB CO LTD

AI summary

A memory device with shortened access time in data reading is provided. The memory device includes a first layer and a second layer positioned above the first layer, the first layer includes a reading circuit, and the second layer includes a first memory cell and a second memory cell. The reading circuit includes a Si transistor. The first memory cell and the second memory cell each include an OS transistor. The first memory cell is electrically connected to the reading circuit, and the second memory cell is electrically connected to the reading circuit. When a first current corresponding to first data retained in the first memory cell flows from the reading circuit to the first memory cell and a second current corresponding to second data retained in the second memory cell flows from the reading circuit to the second memory cell, the reading circuit compares the current amounts of the first current and the second current, and reads the first data.