Non-Volatile Memory Read Current Stability via Post-Program Tuning
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Solution Overview
Problem
Non-volatile memory devices, such as split gate memory cells, face instability in read operations due to random telegraph noise (RTN) caused by electron capture and emission in oxide traps, leading to variations in threshold voltage and read current.
Innovation Solution
A memory device with control circuitry that performs post-program tuning by initially programming memory cells to a target threshold voltage, then adjusting program voltages based on read current measurements to compensate for RTN, ensuring stability and accuracy in read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory cells are programmed to target threshold voltage, then read current stability is improved, but RTN causes threshold voltage variations that degrade read accuracy
Solution Approach 1:
The patent applies preliminary action by performing post-program tuning operations after initial programming to compensate for RTN effects. The system conducts additional read operations and adjusts program voltages based on measured threshold voltage deviations, thereby preemptively correcting RTN-induced inaccuracies before they affect data integrity.
Solution Approach 2:
The patent implements feedback by measuring the actual threshold voltage during read operations and using this information to adjust subsequent programming operations. The system compares measured threshold voltage against target values and modifies program voltage parameters accordingly, creating a closed-loop system that continuously compensates for RTN effects.
2Measurement precision
If post-program tuning is performed to compensate for RTN, then read accuracy is improved, but programming time and process complexity increase
Solution Approach 1:
The patent applies partial action by performing post-program tuning only when necessary, rather than universally for all memory cells. The system identifies cells requiring additional tuning based on initial read operation results and applies corrective programming only to those cells, thereby reducing overall programming time while maintaining accuracy where needed.
Solution Approach 2:
The patent utilizes parameter changes by dynamically adjusting program voltage parameters based on measured threshold voltage deviations. The system modifies voltage magnitude and duration parameters in response to RTN detection, optimizing the tuning process to achieve accurate programming with minimal additional time investment.
3Stability of the object's composition
If multiple programming iterations are performed, then threshold voltage stability is improved, but device complexity and operation time increase
Solution Approach 1:
The patent applies dynamics by making the programming process adaptive and flexible rather than fixed. The system dynamically determines the number of programming iterations needed based on real-time measurements of threshold voltage stability, allowing the process to terminate early when stability criteria are met, thereby reducing complexity while maintaining effectiveness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The post-program tuning technique effectively compensates for RTN, maintaining the control gate threshold voltage within a predetermined tolerance, thereby improving the accuracy and reliability of read operations in non-volatile memory devices.
Implementation Method 1
The floating gate 20 is disposed vertically over and insulated from (and controls the conductivity of) a first portion of the channel region 18
Implementation Method 2
electrons becoming accelerated and heated whereby some of them are injected onto the floating gate 20 by hotelectron injection
Implementation Method 3
A channel region 18 of the substrate is defined between the source/drain regions 14/16. A floating gate 20 is disposed vertically over and insulated from (and controls the conductivity of) a first portion of the channel region 18
Implementation Method 4
Split gate memory cell 10 can be read by placing positive voltages on the select gate 24 (turning on the portion of channel region 18 under the select gate 24) and drain region 16 (and optionally on the erase gate 26 and/or the control gate 22), and sensing current flow through the channel region 18
Data Source
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AI summary
A memory device and method for a non-volatile memory cell having a gate that includes programming the memory cell to an initial program state corresponding to a target read current and a threshold voltage, including applying a program voltage having a first value to the gate, storing the first value in a memory, reading the memory cell in a first read operation using a read voltage applied to the gate that is less than the target threshold voltage to generate a first read current, and subjecting the memory cell to additional programming in response to determining that the first read current is greater than the target read current. The additional programming includes retrieving the first value from the memory, determining a second value greater than the first value, and programming the selected non-volatile memory cell that includes applying a program voltage having the second value to the gate.