Memory Block Read Tracking for Slow Read Disturb Mitigation
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Solution Overview
Problem
Existing memory sub-systems suffer from slow read disturb, which causes adjacent memory cells to discharge voltage slowly, leading to increased error rates and reduced performance due to the need for additional voltage discharge commands, regardless of whether they are issued regularly or only when errors are detected.
Innovation Solution
Identify the trailing read operation by tracking the number of reads and elapsed time for each block, and issue a voltage discharge command only to the block associated with the trailing read to mitigate slow read disturb.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If voltage discharge commands are issued regularly or when errors are detected, then error rates are reduced, but performance is reduced due to additional commands
Solution Approach 1:
The system performs preliminary tracking of read operations and identifies trailing reads before they cause significant slow read disturb effects. By proactively issuing voltage discharge commands after identified trailing reads, the system prevents error accumulation rather than reacting to errors after they occur, thereby reducing error rates while minimizing the number of discharge commands issued.
Solution Approach 2:
The system implements a feedback mechanism by tracking the number of read operations and elapsed time for each block to identify trailing reads. This feedback information is used to intelligently determine when voltage discharge commands are necessary, allowing the system to issue commands only when needed to mitigate slow read disturb, thus balancing error reduction with performance maintenance.
2Reliability
If voltage discharge commands are issued to mitigate slow read disturb, then error rates are reduced, but unnecessary commands increase overhead
Solution Approach 1:
The system applies local quality by tracking and identifying trailing reads at the block level rather than applying uniform voltage discharge commands across all blocks. By issuing discharge commands only to specific blocks that have been identified as trailing reads, the system locally targets the exact areas needing mitigation, reducing overall command overhead while maintaining error reduction effectiveness.
3Productivity
If trailing read identification is implemented by tracking reads and time, then voltage discharge commands are minimized, but tracking overhead is introduced
Solution Approach 1:
The system implements self-service by having the memory sub-system automatically track its own read operations and elapsed time for each block. This self-tracking mechanism enables the system to autonomously identify trailing reads and determine when voltage discharge commands are needed without external intervention, minimizing command overhead while the tracking overhead is offset by the elimination of unnecessary discharge commands.
Data Source
AI summary
Disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include, responsive to receiving a read request to perform a read operation on a block of the memory device, incrementing a counter associated with the block to track a number of read operations performed on the block; setting a timer associated with the block to an initial value; determining that respective values of the counter and the timer are indicative of a minimum number of read operations performed on the block; and issuing a voltage discharge command to the block, wherein issuing the voltage discharge command results in the block reaching a ground voltage.